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Commit da3601a5 authored by Greg Ungerer's avatar Greg Ungerer
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m68knommu: add support for second interrupt controller of ColdFire 5249 



The ColdFire 5249 CPU has a second (compleletly different) interrupt
controller. It is the only ColdFire CPU that has this type. It controlls
GPIO interrupts amongst a number of interrupts from other internal
peripherals. Add support code for it.

Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
parent 3945ca0f

arch/m68k/include/asm/m5249sim.h

+18 −2
Original line number Diff line number Diff line
@@ -106,6 +106,22 @@ 
#define	MCFSIM2_IDECONFIG1	0x18c		/* IDEconfig1 */

#define	MCFSIM2_IDECONFIG2	0x190		/* IDEconfig2 */



/*

 * Define the base interrupt for the second interrupt controller.

 * We set it to 128, out of the way of the base interrupts, and plenty

 * of room for its 64 interrupts.

 */

#define	MCFINTC2_VECBASE	128



#define	MCFINTC2_GPIOIRQ0	(MCFINTC2_VECBASE + 32)

#define	MCFINTC2_GPIOIRQ1	(MCFINTC2_VECBASE + 33)

#define	MCFINTC2_GPIOIRQ2	(MCFINTC2_VECBASE + 34)

#define	MCFINTC2_GPIOIRQ3	(MCFINTC2_VECBASE + 35)

#define	MCFINTC2_GPIOIRQ4	(MCFINTC2_VECBASE + 36)

#define	MCFINTC2_GPIOIRQ5	(MCFINTC2_VECBASE + 37)

#define	MCFINTC2_GPIOIRQ6	(MCFINTC2_VECBASE + 38)

#define	MCFINTC2_GPIOIRQ7	(MCFINTC2_VECBASE + 39)



/*

 * Generic GPIO support

 */
@@ -135,9 +151,9 @@ 
	subql	#1,%a1				/* get MBAR2 address in a1 */



	/*

	 *      Move secondary interrupts to base at 128.

	 *      Move secondary interrupts to their base (128).

	 */

	moveb	#0x80,%d0

	moveb	#MCFINTC2_VECBASE,%d0

	moveb	%d0,0x16b(%a1)			/* interrupt base register */



	/*

arch/m68knommu/platform/5249/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -14,5 +14,5 @@ 


asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1



obj-y := config.o gpio.o

obj-y := config.o gpio.o intc2.o

arch/m68knommu/platform/5249/intc2.c

0 → 100644
+59 −0
Original line number Diff line number Diff line 
/*

 * intc2.c  -- support for the 2nd INTC controller of the 5249

 *

 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file COPYING in the main directory of this archive

 * for more details.

 */



#include <linux/types.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/interrupt.h>

#include <linux/irq.h>

#include <linux/io.h>

#include <asm/coldfire.h>

#include <asm/mcfsim.h>



static void intc2_irq_gpio_mask(unsigned int irq)

{

	u32 imr;

	imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);

	imr &= ~(0x1 << (irq - MCFINTC2_GPIOIRQ0));

	writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);

}



static void intc2_irq_gpio_unmask(unsigned int irq)

{

	u32 imr;

	imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);

	imr |= (0x1 << (irq - MCFINTC2_GPIOIRQ0));

	writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);

}



static void intc2_irq_gpio_ack(unsigned int irq)

{

	writel(0x1 << (irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);

}



static struct irq_chip intc2_irq_gpio_chip = {

	.name		= "CF-INTC2",

	.mask		= intc2_irq_gpio_mask,

	.unmask		= intc2_irq_gpio_unmask,

	.ack		= intc2_irq_gpio_ack,

};



static int __init mcf_intc2_init(void)

{

	int irq;



	/* GPIO interrupt sources */

	for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++)

		irq_desc[irq].chip = &intc2_irq_gpio_chip;



	return 0;

}



arch_initcall(mcf_intc2_init);