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Commit d978006a authored by Paul Mundt's avatar Paul Mundt
Browse files

Merge branch 'sh/dynamic-irq-cleanup' into sh-latest 



Conflicts:
	drivers/sh/intc/dynamic.c

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parents f21efd45 123df01e

arch/sh/boards/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ config SH_7721_SOLUTION_ENGINE 
config SH_7722_SOLUTION_ENGINE

	bool "SolutionEngine7722"

	select SOLUTION_ENGINE

	select GENERIC_IRQ_CHIP

	select IRQ_DOMAIN

	depends on CPU_SUBTYPE_SH7722

	help

	  Select 7722 SolutionEngine if configuring for a Hitachi SH772
@@ -80,6 +82,8 @@ config SH_7780_SOLUTION_ENGINE 
config SH_7343_SOLUTION_ENGINE

	bool "SolutionEngine7343"

	select SOLUTION_ENGINE

	select GENERIC_IRQ_CHIP

	select IRQ_DOMAIN

	depends on CPU_SUBTYPE_SH7343

	help

	  Select 7343 SolutionEngine if configuring for a Hitachi
@@ -295,6 +299,7 @@ config SH_X3PROTO 
	bool "SH-X3 Prototype board"

	depends on CPU_SUBTYPE_SHX3

	select NO_IOPORT if !PCI

	select IRQ_DOMAIN



config SH_MAGIC_PANEL_R2

	bool "Magic Panel R2"

arch/sh/boards/mach-dreamcast/irq.c

+11 −21
Original line number Diff line number Diff line
@@ -8,10 +8,11 @@ 
 * This file is part of the LinuxDC project (www.linuxdc.org)

 * Released under the terms of the GNU GPL v2.0

 */



#include <linux/irq.h>

#include <linux/io.h>

#include <asm/irq.h>

#include <linux/irq.h>

#include <linux/export.h>

#include <linux/err.h>

#include <mach/sysasic.h>



/*
@@ -141,26 +142,15 @@ int systemasic_irq_demux(int irq) 


void systemasic_irq_init(void)

{

	int i, nid = cpu_to_node(boot_cpu_data);

	int irq_base, i;



	/* Assign all virtual IRQs to the System ASIC int. handler */

	for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) {

		unsigned int irq;



		irq = create_irq_nr(i, nid);

		if (unlikely(irq == 0)) {

			pr_err("%s: failed hooking irq %d for systemasic\n",

			       __func__, i);

			return;

		}



		if (unlikely(irq != i)) {

			pr_err("%s: got irq %d but wanted %d, bailing.\n",

			       __func__, irq, i);

			destroy_irq(irq);

	irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE,

				   HW_EVENT_IRQ_MAX - HW_EVENT_IRQ_BASE, -1);

	if (IS_ERR_VALUE(irq_base)) {

		pr_err("%s: failed hooking irqs\n", __func__);

		return;

	}



	for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)

		irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq);

}
 
}

arch/sh/boards/mach-se/7343/irq.c

+86 −43
Original line number Diff line number Diff line 
/*

 * linux/arch/sh/boards/se/7343/irq.c

 * Hitachi UL SolutionEngine 7343 FPGA IRQ Support.

 *

 * Copyright (C) 2008  Yoshihiro Shimoda

 * Copyright (C) 2012  Paul Mundt

 *

 * Based on linux/arch/sh/boards/se/7722/irq.c

 * Based on linux/arch/sh/boards/se/7343/irq.c

 * Copyright (C) 2007  Nobuhiro Iwamatsu

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#define DRV_NAME "SE7343-FPGA"

#define pr_fmt(fmt) DRV_NAME ": " fmt



#define irq_reg_readl	ioread16

#define irq_reg_writel	iowrite16



#include <linux/init.h>

#include <linux/irq.h>

#include <linux/interrupt.h>

#include <linux/irqdomain.h>

#include <linux/io.h>

#include <asm/sizes.h>

#include <mach-se/mach/se7343.h>



unsigned int se7343_fpga_irq[SE7343_FPGA_IRQ_NR] = { 0, };

#define PA_CPLD_BASE_ADDR	0x11400000

#define PA_CPLD_ST_REG		0x08	/* CPLD Interrupt status register */

#define PA_CPLD_IMSK_REG	0x0a	/* CPLD Interrupt mask register */



static void disable_se7343_irq(struct irq_data *data)

{

	unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);

	__raw_writew(__raw_readw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);

}

static void __iomem *se7343_irq_regs;

struct irq_domain *se7343_irq_domain;



static void enable_se7343_irq(struct irq_data *data)

static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)

{

	unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);

	__raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);

}

	struct irq_data *data = irq_get_irq_data(irq);

	struct irq_chip *chip = irq_data_get_irq_chip(data);

	unsigned long mask;

	int bit;



static struct irq_chip se7343_irq_chip __read_mostly = {

	.name		= "SE7343-FPGA",

	.irq_mask	= disable_se7343_irq,

	.irq_unmask	= enable_se7343_irq,

};

	chip->irq_mask_ack(data);



static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)

	mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG);



	for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR)

		generic_handle_irq(irq_linear_revmap(se7343_irq_domain, bit));



	chip->irq_unmask(data);

}



static void __init se7343_domain_init(void)

{

	unsigned short intv = __raw_readw(PA_CPLD_ST);

	unsigned int ext_irq = 0;

	int i;



	intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;

	se7343_irq_domain = irq_domain_add_linear(NULL, SE7343_FPGA_IRQ_NR,

						  &irq_domain_simple_ops, NULL);

	if (unlikely(!se7343_irq_domain)) {

		printk("Failed to get IRQ domain\n");

		return;

	}



	for (; intv; intv >>= 1, ext_irq++) {

		if (!(intv & 1))

			continue;

	for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {

		int irq = irq_create_mapping(se7343_irq_domain, i);



		generic_handle_irq(se7343_fpga_irq[ext_irq]);

		if (unlikely(irq == 0)) {

			printk("Failed to allocate IRQ %d\n", i);

			return;

		}

	}

}



/*

 * Initialize IRQ setting

 */

void __init init_7343se_IRQ(void)

static void __init se7343_gc_init(void)

{

	int i, irq;

	struct irq_chip_generic *gc;

	struct irq_chip_type *ct;

	unsigned int irq_base;



	__raw_writew(0, PA_CPLD_IMSK);	/* disable all irqs */

	__raw_writew(0x2000, 0xb03fffec);	/* mrshpc irq enable */

	irq_base = irq_linear_revmap(se7343_irq_domain, 0);



	for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {

		irq = create_irq();

		if (irq < 0)

	gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7343_irq_regs,

				    handle_level_irq);

	if (unlikely(!gc))

		return;

		se7343_fpga_irq[i] = irq;



		irq_set_chip_and_handler_name(se7343_fpga_irq[i],

					      &se7343_irq_chip,

					      handle_level_irq,

					      "level");

	ct = gc->chip_types;

	ct->chip.irq_mask = irq_gc_mask_set_bit;

	ct->chip.irq_unmask = irq_gc_mask_clr_bit;



		irq_set_chip_data(se7343_fpga_irq[i], (void *)i);

	}

	ct->regs.mask = PA_CPLD_IMSK_REG;



	irq_setup_generic_chip(gc, IRQ_MSK(SE7343_FPGA_IRQ_NR),

			       IRQ_GC_INIT_MASK_CACHE,

			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);



	irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);

	irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);



	irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);

	irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);



	irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);

	irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);



	irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);

	irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);

}



/*

 * Initialize IRQ setting

 */

void __init init_7343se_IRQ(void)

{

	se7343_irq_regs = ioremap(PA_CPLD_BASE_ADDR, SZ_16);

	if (unlikely(!se7343_irq_regs)) {

		pr_err("Failed to remap CPLD\n");

		return;

	}



	/*

	 * All FPGA IRQs disabled by default

	 */

	iowrite16(0, se7343_irq_regs + PA_CPLD_IMSK_REG);



	__raw_writew(0x2000, 0xb03fffec);	/* mrshpc irq enable */



	se7343_domain_init();

	se7343_gc_init();

}

arch/sh/boards/mach-se/7343/setup.c

+6 −4
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
#include <linux/serial_reg.h>

#include <linux/usb/isp116x.h>

#include <linux/delay.h>

#include <linux/irqdomain.h>

#include <asm/machvec.h>

#include <mach-se/mach/se7343.h>

#include <asm/heartbeat.h>
@@ -145,11 +146,12 @@ static struct platform_device *sh7343se_platform_devices[] __initdata = { 
static int __init sh7343se_devices_setup(void)

{

	/* Wire-up dynamic vectors */

	serial_platform_data[0].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTA];

	serial_platform_data[1].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTB];



	serial_platform_data[0].irq = irq_find_mapping(se7343_irq_domain,

						       SE7343_FPGA_IRQ_UARTA);

	serial_platform_data[1].irq = irq_find_mapping(se7343_irq_domain,

						       SE7343_FPGA_IRQ_UARTB);

	usb_resources[2].start = usb_resources[2].end =

		se7343_fpga_irq[SE7343_FPGA_IRQ_USB];

		irq_find_mapping(se7343_irq_domain, SE7343_FPGA_IRQ_USB);



	return platform_add_devices(sh7343se_platform_devices,

				    ARRAY_SIZE(sh7343se_platform_devices));

arch/sh/boards/mach-se/7722/irq.c

+85 −46
Original line number Diff line number Diff line 
/*

 * linux/arch/sh/boards/se/7722/irq.c

 * Hitachi UL SolutionEngine 7722 FPGA IRQ Support.

 *

 * Copyright (C) 2007  Nobuhiro Iwamatsu

 *

 * Hitachi UL SolutionEngine 7722 Support.

 * Copyright (C) 2012  Paul Mundt

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#define DRV_NAME "SE7722-FPGA"

#define pr_fmt(fmt) DRV_NAME ": " fmt



#define irq_reg_readl	ioread16

#define irq_reg_writel	iowrite16



#include <linux/init.h>

#include <linux/irq.h>

#include <linux/interrupt.h>

#include <asm/irq.h>

#include <asm/io.h>

#include <linux/irqdomain.h>

#include <linux/io.h>

#include <linux/err.h>

#include <asm/sizes.h>

#include <mach-se/mach/se7722.h>



unsigned int se7722_fpga_irq[SE7722_FPGA_IRQ_NR] = { 0, };

#define IRQ01_BASE_ADDR	0x11800000

#define IRQ01_MODE_REG	0

#define IRQ01_STS_REG	4

#define IRQ01_MASK_REG	8



static void disable_se7722_irq(struct irq_data *data)

{

	unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);

	__raw_writew(__raw_readw(IRQ01_MASK) | 1 << bit, IRQ01_MASK);

}

static void __iomem *se7722_irq_regs;

struct irq_domain *se7722_irq_domain;



static void enable_se7722_irq(struct irq_data *data)

static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)

{

	unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);

	__raw_writew(__raw_readw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK);

}

	struct irq_data *data = irq_get_irq_data(irq);

	struct irq_chip *chip = irq_data_get_irq_chip(data);

	unsigned long mask;

	int bit;



static struct irq_chip se7722_irq_chip __read_mostly = {

	.name		= "SE7722-FPGA",

	.irq_mask	= disable_se7722_irq,

	.irq_unmask	= enable_se7722_irq,

};

	chip->irq_mask_ack(data);



static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)

	mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);



	for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)

		generic_handle_irq(irq_linear_revmap(se7722_irq_domain, bit));



	chip->irq_unmask(data);

}



static void __init se7722_domain_init(void)

{

	unsigned short intv = __raw_readw(IRQ01_STS);

	unsigned int ext_irq = 0;

	int i;



	intv &= (1 << SE7722_FPGA_IRQ_NR) - 1;

	se7722_irq_domain = irq_domain_add_linear(NULL, SE7722_FPGA_IRQ_NR,

						  &irq_domain_simple_ops, NULL);

	if (unlikely(!se7722_irq_domain)) {

		printk("Failed to get IRQ domain\n");

		return;

	}



	for (; intv; intv >>= 1, ext_irq++) {

		if (!(intv & 1))

			continue;

	for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {

		int irq = irq_create_mapping(se7722_irq_domain, i);



		generic_handle_irq(se7722_fpga_irq[ext_irq]);

		if (unlikely(irq == 0)) {

			printk("Failed to allocate IRQ %d\n", i);

			return;

		}

	}

}



/*

 * Initialize IRQ setting

 */

void __init init_se7722_IRQ(void)

static void __init se7722_gc_init(void)

{

	int i, irq;

	struct irq_chip_generic *gc;

	struct irq_chip_type *ct;

	unsigned int irq_base;



	__raw_writew(0, IRQ01_MASK);       /* disable all irqs */

	__raw_writew(0x2000, 0xb03fffec);  /* mrshpc irq enable */

	irq_base = irq_linear_revmap(se7722_irq_domain, 0);



	for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {

		irq = create_irq();

		if (irq < 0)

	gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs,

				    handle_level_irq);

	if (unlikely(!gc))

		return;

		se7722_fpga_irq[i] = irq;



		irq_set_chip_and_handler_name(se7722_fpga_irq[i],

					      &se7722_irq_chip,

					      handle_level_irq,

					      "level");

	ct = gc->chip_types;

	ct->chip.irq_mask = irq_gc_mask_set_bit;

	ct->chip.irq_unmask = irq_gc_mask_clr_bit;



		irq_set_chip_data(se7722_fpga_irq[i], (void *)i);

	}

	ct->regs.mask = IRQ01_MASK_REG;



	irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR),

			       IRQ_GC_INIT_MASK_CACHE,

			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);



	irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);

	irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
@@ -81,3 +98,25 @@ void __init init_se7722_IRQ(void) 
	irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);

	irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);

}



/*

 * Initialize FPGA IRQs

 */

void __init init_se7722_IRQ(void)

{

	se7722_irq_regs = ioremap(IRQ01_BASE_ADDR, SZ_16);

	if (unlikely(!se7722_irq_regs)) {

		printk("Failed to remap IRQ01 regs\n");

		return;

	}



	/*

	 * All FPGA IRQs disabled by default

	 */

	iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG);



	__raw_writew(0x2000, 0xb03fffec);  /* mrshpc irq enable */



	se7722_domain_init();

	se7722_gc_init();

}