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Commit d91fb219 authored by Phani Kumar Uppalapati's avatar Phani Kumar Uppalapati Committed by Matt Wagantall
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mfd: wcd9335: Update wcd9335 codec register defaults 



Update wcd9335 codec register tables with correct
default values.

Change-Id: Ib994fad420afffa1d369ab164584f5f19f8c4712
Signed-off-by: default avatarPhani Kumar Uppalapati <phaniu@codeaurora.org>
parent 8f8bcd4e

drivers/mfd/wcd9335-regmap.c

+38 −37
Original line number Diff line number Diff line
@@ -414,8 +414,8 @@ static const struct reg_default wcd9335_defaults[] = { 
	{ WCD9335_ANA_RCO                               , 0x30 },

	{ WCD9335_ANA_BUCK_VOUT_A                       , 0xb4 },

	{ WCD9335_ANA_BUCK_VOUT_D                       , 0xb4 },

	{ WCD9335_ANA_BUCK_RAMP_CAL_CTL                 , 0x00 },

	{ WCD9335_ANA_BUCK_RAMP_CAL_STATUS              , 0x00 },

	{ WCD9335_ANA_BUCK_CTL                          , 0x00 },

	{ WCD9335_ANA_BUCK_STATUS                       , 0xe0 },

	{ WCD9335_ANA_RX_SUPPLIES                       , 0x00 },

	{ WCD9335_ANA_HPH                               , 0x00 },

	{ WCD9335_ANA_EAR                               , 0x00 },
@@ -429,7 +429,7 @@ static const struct reg_default wcd9335_defaults[] = { 
	{ WCD9335_ANA_AMIC5                             , 0x20 },

	{ WCD9335_ANA_AMIC6                             , 0x00 },

	{ WCD9335_ANA_MBHC_MECH                         , 0x39 },

	{ WCD9335_ANA_MBHC_ELECT                        , 0x38 },

	{ WCD9335_ANA_MBHC_ELECT                        , 0x08 },

	{ WCD9335_ANA_MBHC_ZDET                         , 0x00 },

	{ WCD9335_ANA_MBHC_RESULT_1                     , 0x00 },

	{ WCD9335_ANA_MBHC_RESULT_2                     , 0x00 },
@@ -449,7 +449,7 @@ static const struct reg_default wcd9335_defaults[] = { 
	{ WCD9335_ANA_MICB4                             , 0x10 },

	{ WCD9335_ANA_VBADC                             , 0x00 },

	{ WCD9335_BIAS_CTL                              , 0x28 },

	{ WCD9335_BIAS_VBG_FINE_ADJ                     , 0x51 },

	{ WCD9335_BIAS_VBG_FINE_ADJ                     , 0x55 },

	{ WCD9335_CLOCK_TEST_CTL                        , 0x00 },

	{ WCD9335_RCO_CTRL_1                            , 0x44 },

	{ WCD9335_RCO_CTRL_2                            , 0x44 },
@@ -462,30 +462,30 @@ static const struct reg_default wcd9335_defaults[] = { 
	{ WCD9335_RCO_CAL_OUT_3                         , 0x00 },

	{ WCD9335_RCO_CAL_OUT_4                         , 0x00 },

	{ WCD9335_RCO_CAL_OUT_5                         , 0x00 },

	{ WCD9335_SIDO_SIDO_MODE_1                      , 0x00 },

	{ WCD9335_SIDO_SIDO_MODE_2                      , 0xff },

	{ WCD9335_SIDO_SIDO_MODE_1                      , 0x84 },

	{ WCD9335_SIDO_SIDO_MODE_2                      , 0xfe },

	{ WCD9335_SIDO_SIDO_MODE_3                      , 0xf6 },

	{ WCD9335_SIDO_SIDO_MODE_4                      , 0x00 },

	{ WCD9335_SIDO_SIDO_MODE_4                      , 0x56 },

	{ WCD9335_SIDO_SIDO_VCL_1                       , 0x00 },

	{ WCD9335_SIDO_SIDO_VCL_2                       , 0x6c },

	{ WCD9335_SIDO_SIDO_VCL_3                       , 0x62 },

	{ WCD9335_SIDO_SIDO_VCL_3                       , 0x44 },

	{ WCD9335_SIDO_SIDO_CCL_1                       , 0x57 },

	{ WCD9335_SIDO_SIDO_CCL_2                       , 0x6c },

	{ WCD9335_SIDO_SIDO_CCL_3                       , 0x6d },

	{ WCD9335_SIDO_SIDO_CCL_4                       , 0x62 },

	{ WCD9335_SIDO_SIDO_CCL_5                       , 0x6c },

	{ WCD9335_SIDO_SIDO_CCL_6                       , 0x6c },

	{ WCD9335_SIDO_SIDO_CCL_3                       , 0x2d },

	{ WCD9335_SIDO_SIDO_CCL_4                       , 0x61 },

	{ WCD9335_SIDO_SIDO_CCL_5                       , 0x6d },

	{ WCD9335_SIDO_SIDO_CCL_6                       , 0x60 },

	{ WCD9335_SIDO_SIDO_CCL_7                       , 0x6f },

	{ WCD9335_SIDO_SIDO_CCL_8                       , 0x6c },

	{ WCD9335_SIDO_SIDO_CCL_9                       , 0x6e },

	{ WCD9335_SIDO_SIDO_CCL_10                      , 0x6c },

	{ WCD9335_SIDO_SIDO_FILTER_1                    , 0x89 },

	{ WCD9335_SIDO_SIDO_FILTER_2                    , 0xa2 },

	{ WCD9335_SIDO_SIDO_FILTER_1                    , 0x92 },

	{ WCD9335_SIDO_SIDO_FILTER_2                    , 0x54 },

	{ WCD9335_SIDO_SIDO_DRIVER_1                    , 0x77 },

	{ WCD9335_SIDO_SIDO_DRIVER_2                    , 0x77 },

	{ WCD9335_SIDO_SIDO_DRIVER_3                    , 0x77 },

	{ WCD9335_SIDO_SIDO_CAL_CODE_EXT_1              , 0x00 },

	{ WCD9335_SIDO_SIDO_CAL_CODE_EXT_2              , 0x00 },

	{ WCD9335_SIDO_SIDO_CAL_CODE_EXT_1              , 0x9c },

	{ WCD9335_SIDO_SIDO_CAL_CODE_EXT_2              , 0x82 },

	{ WCD9335_SIDO_SIDO_CAL_CODE_OUT_1              , 0x00 },

	{ WCD9335_SIDO_SIDO_CAL_CODE_OUT_2              , 0x00 },

	{ WCD9335_SIDO_SIDO_TEST_1                      , 0x00 },
@@ -501,7 +501,7 @@ static const struct reg_default wcd9335_defaults[] = { 
	{ WCD9335_VBADC_IBIAS_FE                        , 0x54 },

	{ WCD9335_VBADC_BIAS_ADC                        , 0x51 },

	{ WCD9335_VBADC_FE_CTRL                         , 0x1c },

	{ WCD9335_VBADC_ADC_REF                         , 0xb0 },

	{ WCD9335_VBADC_ADC_REF                         , 0x20 },

	{ WCD9335_VBADC_ADC_IO                          , 0x80 },

	{ WCD9335_VBADC_ADC_SAR                         , 0xff },

	{ WCD9335_VBADC_DEBUG                           , 0x00 },
@@ -533,7 +533,7 @@ static const struct reg_default wcd9335_defaults[] = { 
	{ WCD9335_TX_COM_TXFE_DIV_STOP_12P288M          , 0xff },

	{ WCD9335_TX_1_2_TEST_EN                        , 0xcc },

	{ WCD9335_TX_1_2_ADC_IB                         , 0x09 },

	{ WCD9335_TX_1_2_ATEST_REFCTL                   , 0x00 },

	{ WCD9335_TX_1_2_ATEST_REFCTL                   , 0x08 },

	{ WCD9335_TX_1_2_TEST_CTL                       , 0x38 },

	{ WCD9335_TX_1_2_TEST_BLK_EN                    , 0xff },

	{ WCD9335_TX_1_2_TXFE_CLKDIV                    , 0x00 },
@@ -541,7 +541,7 @@ static const struct reg_default wcd9335_defaults[] = { 
	{ WCD9335_TX_1_2_SAR2_ERR                       , 0x00 },

	{ WCD9335_TX_3_4_TEST_EN                        , 0xcc },

	{ WCD9335_TX_3_4_ADC_IB                         , 0x09 },

	{ WCD9335_TX_3_4_ATEST_REFCTL                   , 0x00 },

	{ WCD9335_TX_3_4_ATEST_REFCTL                   , 0x08 },

	{ WCD9335_TX_3_4_TEST_CTL                       , 0x38 },

	{ WCD9335_TX_3_4_TEST_BLK_EN                    , 0xff },

	{ WCD9335_TX_3_4_TXFE_CLKDIV                    , 0x00 },
@@ -549,25 +549,25 @@ static const struct reg_default wcd9335_defaults[] = { 
	{ WCD9335_TX_3_4_SAR2_ERR                       , 0x00 },

	{ WCD9335_TX_5_6_TEST_EN                        , 0xcc },

	{ WCD9335_TX_5_6_ADC_IB                         , 0x09 },

	{ WCD9335_TX_5_6_ATEST_REFCTL                   , 0x00 },

	{ WCD9335_TX_5_6_ATEST_REFCTL                   , 0x08 },

	{ WCD9335_TX_5_6_TEST_CTL                       , 0x38 },

	{ WCD9335_TX_5_6_TEST_BLK_EN                    , 0xff },

	{ WCD9335_TX_5_6_TXFE_CLKDIV                    , 0x00 },

	{ WCD9335_TX_5_6_SAR1_ERR                       , 0x00 },

	{ WCD9335_TX_5_6_SAR2_ERR                       , 0x00 },

	{ WCD9335_CLASSH_MODE_1                         , 0x20 },

	{ WCD9335_CLASSH_MODE_1                         , 0x40 },

	{ WCD9335_CLASSH_MODE_2                         , 0x3a },

	{ WCD9335_CLASSH_MODE_3                         , 0x00 },

	{ WCD9335_CLASSH_CTRL_VCL_1                     , 0x70 },

	{ WCD9335_CLASSH_CTRL_VCL_2                     , 0xa2 },

	{ WCD9335_CLASSH_CTRL_CCL_1                     , 0x51 },

	{ WCD9335_CLASSH_CTRL_CCL_2                     , 0xdc },

	{ WCD9335_CLASSH_CTRL_CCL_3                     , 0xa5 },

	{ WCD9335_CLASSH_CTRL_CCL_2                     , 0x80 },

	{ WCD9335_CLASSH_CTRL_CCL_3                     , 0x80 },

	{ WCD9335_CLASSH_CTRL_CCL_4                     , 0x51 },

	{ WCD9335_CLASSH_CTRL_CCL_5                     , 0x10 },

	{ WCD9335_CLASSH_CTRL_CCL_5                     , 0x00 },

	{ WCD9335_CLASSH_BUCK_TMUX_A_D                  , 0x00 },

	{ WCD9335_CLASSH_TBD_1                          , 0x00 },

	{ WCD9335_CLASSH_TBD_2                          , 0x00 },

	{ WCD9335_CLASSH_BUCK_SW_DRV_CNTL               , 0x77 },

	{ WCD9335_CLASSH_SPARE                          , 0x00 },

	{ WCD9335_FLYBACK_EN                            , 0x4e },

	{ WCD9335_FLYBACK_VNEG_CTRL_1                   , 0x67 },

	{ WCD9335_FLYBACK_VNEG_CTRL_2                   , 0x45 },
@@ -605,12 +605,12 @@ static const struct reg_default wcd9335_defaults[] = { 
	{ WCD9335_RX_BIAS_FLYB_ERRAMP                   , 0x40 },

	{ WCD9335_RX_BIAS_FLYB_BUFF                     , 0xaa },

	{ WCD9335_RX_BIAS_FLYB_MID_RST                  , 0x44 },

	{ WCD9335_HPH_L_STATUS                          , 0x00 },

	{ WCD9335_HPH_R_STATUS                          , 0x00 },

	{ WCD9335_HPH_CNP_EN                            , 0xa0 },

	{ WCD9335_HPH_L_STATUS                          , 0x04 },

	{ WCD9335_HPH_R_STATUS                          , 0x04 },

	{ WCD9335_HPH_CNP_EN                            , 0x80 },

	{ WCD9335_HPH_CNP_WG_CTL                        , 0xda },

	{ WCD9335_HPH_CNP_WG_TIME                       , 0x15 },

	{ WCD9335_HPH_OCP_CTL                           , 0x2a },

	{ WCD9335_HPH_OCP_CTL                           , 0x28 },

	{ WCD9335_HPH_AUTO_CHOP                         , 0x12 },

	{ WCD9335_HPH_CHOP_CTL                          , 0x83 },

	{ WCD9335_HPH_PA_CTL1                           , 0x46 },
@@ -624,28 +624,29 @@ static const struct reg_default wcd9335_defaults[] = { 
	{ WCD9335_HPH_RDAC_CLK_CTL1                     , 0x99 },

	{ WCD9335_HPH_RDAC_CLK_CTL2                     , 0x9b },

	{ WCD9335_HPH_RDAC_LDO_CTL                      , 0x00 },

	{ WCD9335_HPH_RDAC_CHOP_CLK_LP_CTL              , 0x00 },

	{ WCD9335_HPH_REFBUFF_UHQA_CTL                  , 0xa8 },

	{ WCD9335_HPH_REFBUFF_LP_CTL                    , 0x00 },

	{ WCD9335_HPH_L_DAC_CTL                         , 0x00 },

	{ WCD9335_HPH_R_DAC_CTL                         , 0x00 },

	{ WCD9335_EAR_EN_REG                            , 0x00 },

	{ WCD9335_EAR_CMBUFF                            , 0x05 },

	{ WCD9335_EAR_EN_REG                            , 0x60 },

	{ WCD9335_EAR_CMBUFF                            , 0x0d },

	{ WCD9335_EAR_ICTL                              , 0x40 },

	{ WCD9335_EAR_EN_DBG_CTL                        , 0x00 },

	{ WCD9335_EAR_CNP                               , 0xca },

	{ WCD9335_EAR_CNP                               , 0xe0 },

	{ WCD9335_EAR_DAC_CTL_ATEST                     , 0x00 },

	{ WCD9335_EAR_STATUS_REG                        , 0x04 },

	{ WCD9335_EAR_OUT_SHORT                         , 0x00 },

	{ WCD9335_DIFF_LO_MISC                          , 0x00 },

	{ WCD9335_DIFF_LO_MISC                          , 0x03 },

	{ WCD9335_DIFF_LO_LO2_COMPANDER                 , 0x00 },

	{ WCD9335_DIFF_LO_LO1_COMPANDER                 , 0x00 },

	{ WCD9335_DIFF_LO_COMMON                        , 0x40 },

	{ WCD9335_DIFF_LO_BYPASS_EN                     , 0x00 },

	{ WCD9335_DIFF_LO_CNP                           , 0x00 },

	{ WCD9335_DIFF_LO_CNP                           , 0x20 },

	{ WCD9335_DIFF_LO_CORE_OUT_PROG                 , 0x00 },

	{ WCD9335_DIFF_LO_LDO_OUT_PROG                  , 0x00 },

	{ WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ         , 0x00 },

	{ WCD9335_DIFF_LO_COM_PA_FREQ                   , 0x00 },

	{ WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ         , 0x9b },

	{ WCD9335_DIFF_LO_COM_PA_FREQ                   , 0xb0 },

	{ WCD9335_DIFF_LO_RESERVED_REG                  , 0x60 },

	{ WCD9335_DIFF_LO_LO1_STATUS_1                  , 0x00 },

	{ WCD9335_DIFF_LO_LO1_STATUS_2                  , 0x00 },

drivers/mfd/wcd9335-tables.c

+5 −4
Original line number Diff line number Diff line
@@ -417,8 +417,8 @@ const u8 wcd9335_page6_reg_readable[WCD9335_PAGE_SIZE] = { 
	[WCD9335_REG(WCD9335_ANA_RCO)] = 1,

	[WCD9335_REG(WCD9335_ANA_BUCK_VOUT_A)] = 1,

	[WCD9335_REG(WCD9335_ANA_BUCK_VOUT_D)] = 1,

	[WCD9335_REG(WCD9335_ANA_BUCK_RAMP_CAL_CTL)] = 1,

	[WCD9335_REG(WCD9335_ANA_BUCK_RAMP_CAL_STATUS)] = 1,

	[WCD9335_REG(WCD9335_ANA_BUCK_CTL)] = 1,

	[WCD9335_REG(WCD9335_ANA_BUCK_STATUS)] = 1,

	[WCD9335_REG(WCD9335_ANA_RX_SUPPLIES)] = 1,

	[WCD9335_REG(WCD9335_ANA_HPH)] = 1,

	[WCD9335_REG(WCD9335_ANA_EAR)] = 1,
@@ -569,8 +569,8 @@ const u8 wcd9335_page6_reg_readable[WCD9335_PAGE_SIZE] = { 
	[WCD9335_REG(WCD9335_CLASSH_CTRL_CCL_4)] = 1,

	[WCD9335_REG(WCD9335_CLASSH_CTRL_CCL_5)] = 1,

	[WCD9335_REG(WCD9335_CLASSH_BUCK_TMUX_A_D)] = 1,

	[WCD9335_REG(WCD9335_CLASSH_TBD_1)] = 1,

	[WCD9335_REG(WCD9335_CLASSH_TBD_2)] = 1,

	[WCD9335_REG(WCD9335_CLASSH_BUCK_SW_DRV_CNTL)] = 1,

	[WCD9335_REG(WCD9335_CLASSH_SPARE)] = 1,

	[WCD9335_REG(WCD9335_FLYBACK_EN)] = 1,

	[WCD9335_REG(WCD9335_FLYBACK_VNEG_CTRL_1)] = 1,

	[WCD9335_REG(WCD9335_FLYBACK_VNEG_CTRL_2)] = 1,
@@ -627,6 +627,7 @@ const u8 wcd9335_page6_reg_readable[WCD9335_PAGE_SIZE] = { 
	[WCD9335_REG(WCD9335_HPH_RDAC_CLK_CTL1)] = 1,

	[WCD9335_REG(WCD9335_HPH_RDAC_CLK_CTL2)] = 1,

	[WCD9335_REG(WCD9335_HPH_RDAC_LDO_CTL)] = 1,

	[WCD9335_REG(WCD9335_HPH_RDAC_CHOP_CLK_LP_CTL)] = 1,

	[WCD9335_REG(WCD9335_HPH_REFBUFF_UHQA_CTL)] = 1,

	[WCD9335_REG(WCD9335_HPH_REFBUFF_LP_CTL)] = 1,

	[WCD9335_REG(WCD9335_HPH_L_DAC_CTL)] = 1,

include/linux/mfd/wcd9335/registers.h

+5 −4
Original line number Diff line number Diff line
@@ -429,8 +429,8 @@ enum { 
#define WCD9335_ANA_RCO                                  0x0603

#define WCD9335_ANA_BUCK_VOUT_A                          0x0604

#define WCD9335_ANA_BUCK_VOUT_D                          0x0605

#define WCD9335_ANA_BUCK_RAMP_CAL_CTL                    0x0606

#define WCD9335_ANA_BUCK_RAMP_CAL_STATUS                 0x0607

#define WCD9335_ANA_BUCK_CTL                             0x0606

#define WCD9335_ANA_BUCK_STATUS                          0x0607

#define WCD9335_ANA_RX_SUPPLIES                          0x0608

#define WCD9335_ANA_HPH                                  0x0609

#define WCD9335_ANA_EAR                                  0x060a
@@ -581,8 +581,8 @@ enum { 
#define WCD9335_CLASSH_CTRL_CCL_4                        0x069f

#define WCD9335_CLASSH_CTRL_CCL_5                        0x06a0

#define WCD9335_CLASSH_BUCK_TMUX_A_D                     0x06a1

#define WCD9335_CLASSH_TBD_1                             0x06a2

#define WCD9335_CLASSH_TBD_2                             0x06a3

#define WCD9335_CLASSH_BUCK_SW_DRV_CNTL                  0x06a2

#define WCD9335_CLASSH_SPARE                             0x06a3

#define WCD9335_FLYBACK_EN                               0x06a4

#define WCD9335_FLYBACK_VNEG_CTRL_1                      0x06a5

#define WCD9335_FLYBACK_VNEG_CTRL_2                      0x06a6
@@ -639,6 +639,7 @@ enum { 
#define WCD9335_HPH_RDAC_CLK_CTL1                        0x06d9

#define WCD9335_HPH_RDAC_CLK_CTL2                        0x06da

#define WCD9335_HPH_RDAC_LDO_CTL                         0x06db

#define WCD9335_HPH_RDAC_CHOP_CLK_LP_CTL                 0x06dc

#define WCD9335_HPH_REFBUFF_UHQA_CTL                     0x06dd

#define WCD9335_HPH_REFBUFF_LP_CTL                       0x06de

#define WCD9335_HPH_L_DAC_CTL                            0x06df