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Commit d862ccc5 authored by Mark Brown's avatar Mark Brown Committed by Russell King
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[ARM] 4843/1: Add GCR_CLKBPB for PXA3xx 



The PXA3xx AC97 controller has an additional control bit GCR_CLKBPB
which must be used during cold reset.

Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: default avatareric miao <eric.miao@marvell.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent ceee4f98

include/asm-arm/arch-pxa/pxa-regs.h

+3 −0
Original line number Diff line number Diff line
@@ -520,6 +520,9 @@ 
#define MCCR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */



#define GCR		__REG(0x4050000C)  /* Global Control Register */

#ifdef CONFIG_PXA3xx

#define GCR_CLKBPB	(1 << 31)	/* Internal clock enable */

#endif

#define GCR_nDMAEN	(1 << 24)	/* non DMA Enable */

#define GCR_CDONE_IE	(1 << 19)	/* Command Done Interrupt Enable */

#define GCR_SDONE_IE	(1 << 18)	/* Status Done Interrupt Enable */