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Commit d83d44c0 authored by Paul Bolle's avatar Paul Bolle Committed by Ralf Baechle
Browse files

MIPS: Octeon: Remove checks for CONFIG_CAVIUM_GDB 



Three checks for CONFIG_CAVIUM_GDB were added in v2.6.29. But the
Kconfig symbol CAVIUM_GDB was never added to the tree. Remove these
checks.

Also remove the last reference to octeon_get_boot_debug_flag(). There is
no definition of that function anyway.

Signed-off-by: default avatarPaul Bolle <pebolle@tiscali.nl>
Tested-by: default avatarAndreas Herrmann <andreas.herrmann@caviumnetworks.com&gt;)>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/6976/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 23634fd3

arch/mips/cavium-octeon/setup.c

+0 −11
Original line number Diff line number Diff line
@@ -729,17 +729,6 @@ void __init prom_init(void) 
	octeon_write_lcd("Linux");

#endif



#ifdef CONFIG_CAVIUM_GDB

	/*

	 * When debugging the linux kernel, force the cores to enter

	 * the debug exception handler to break in.

	 */

	if (octeon_get_boot_debug_flag()) {

		cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num());

		cvmx_read_csr(CVMX_CIU_DINT);

	}

#endif



	octeon_setup_delays();



	/*

arch/mips/cavium-octeon/smp.c

+0 −17
Original line number Diff line number Diff line
@@ -218,15 +218,6 @@ void octeon_prepare_cpus(unsigned int max_cpus) 
 */

static void octeon_smp_finish(void)

{

#ifdef CONFIG_CAVIUM_GDB

	unsigned long tmp;

	/* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0

	   to be not masked by this core so we know the signal is received by

	   someone */

	asm volatile ("dmfc0 %0, $22\n"

		      "ori   %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));

#endif



	octeon_user_io_init();



	/* to generate the first CPU timer interrupt */
@@ -239,14 +230,6 @@ static void octeon_smp_finish(void) 
 */

static void octeon_cpus_done(void)

{

#ifdef CONFIG_CAVIUM_GDB

	unsigned long tmp;

	/* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0

	   to be not masked by this core so we know the signal is received by

	   someone */

	asm volatile ("dmfc0 %0, $22\n"

		      "ori   %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));

#endif

}



#ifdef CONFIG_HOTPLUG_CPU

arch/mips/include/asm/octeon/octeon.h

+0 −1
Original line number Diff line number Diff line
@@ -211,7 +211,6 @@ union octeon_cvmemctl { 


extern void octeon_write_lcd(const char *s);

extern void octeon_check_cpu_bist(void);

extern int octeon_get_boot_debug_flag(void);

extern int octeon_get_boot_uart(void);



struct uart_port;