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Commit d837d7de authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: msm: clock: Add the MMSS clock driver support for MSMCOBALT"

parents a27b6961 e9bc236c

Documentation/devicetree/bindings/arm/msm/clock-controller.txt

+1 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ Required properties: 
			"qcom,gcc-cobalt"

			"qcom,cc-debug-cobalt"

			"qcom,gpucc-cobalt"

			"qcom,mmsscc-cobalt"



- reg:			Pairs of physical base addresses and region sizes of

			memory mapped registers.

arch/arm/boot/dts/qcom/msm-arm-smmu-cobalt.dtsi

+3 −3
Original line number Diff line number Diff line 
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -141,8 +141,8 @@ 
			   <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;

		vdd-supply = <&gdsc_bimc_smmu>;

		clocks = <&clock_mmss clk_bimc_smmu_ahb_clk>,

			<&clock_mmss clk_bimc_smmu_axi_clk>;

		clocks = <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>;

		clock-names = "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk";

		#clock-cells = <1>;

		/*

arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi

+8 −8
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -71,14 +71,14 @@ 
		smmu-vdd-supply = <&gdsc_bimc_smmu>;

		camss-vdd-supply = <&gdsc_camss_top>;

		qcom,vdd-names = "smmu-vdd", "camss-vdd";

		clocks = <&clock_mmss clk_camss_top_ahb_clk>,

		clocks = <&clock_mmss clk_mmss_camss_top_ahb_clk>,

			<&clock_mmss clk_fd_core_clk_src>,

			<&clock_mmss clk_fd_core_clk>,

			<&clock_mmss clk_fd_core_uar_clk>,

			<&clock_mmss clk_fd_ahb_clk>,

			<&clock_mmss clk_camss_ahb_clk>,

			<&clock_mmss clk_camss_cpp_axi_clk>,

			<&clock_mmss clk_camss_cpp_vbif_ahb_clk>;

			<&clock_mmss clk_mmss_fd_core_clk>,

			<&clock_mmss clk_mmss_fd_core_uar_clk>,

			<&clock_mmss clk_mmss_fd_ahb_clk>,

			<&clock_mmss clk_mmss_camss_ahb_clk>,

			<&clock_mmss clk_mmss_camss_cpp_axi_clk>,

			<&clock_mmss clk_mmss_camss_cpp_vbif_ahb_clk>;

		clock-names = "camss_top_ahb_clk",

			"fd_core_clk_src", "fd_core_clk",

			"fd_core_uar_clk", "fd_ahb_clk",

arch/arm/boot/dts/qcom/msmcobalt-vidc.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -34,8 +34,8 @@ 
		    <0x14800000 0x80000>;

		reg-names = "reg-base", "mem-base";



		clocks = <&clock_mmss clk_vmem_ahb_clk>,

		       <&clock_mmss clk_vmem_maxi_clk>;

		clocks = <&clock_mmss clk_mmss_vmem_ahb_clk>,

		       <&clock_mmss clk_mmss_vmem_maxi_clk>;

		clock-names = "ahb", "maxi";



		qcom,msm-bus,name = "vmem";

arch/arm/boot/dts/qcom/msmcobalt.dtsi

+20 −20
Original line number Diff line number Diff line
@@ -1339,10 +1339,10 @@ 
		vdd-supply = <&gdsc_venus>;

		qcom,proxy-reg-names = "vdd";



		clocks = <&clock_mmss clk_video_core_clk>,

			 <&clock_mmss clk_video_ahb_clk>,

			 <&clock_mmss clk_video_axi_clk>,

			 <&clock_mmss clk_video_maxi_clk>;

		clocks = <&clock_mmss clk_mmss_video_core_clk>,

			 <&clock_mmss clk_mmss_video_ahb_clk>,

			 <&clock_mmss clk_mmss_video_axi_clk>,

			 <&clock_mmss clk_mmss_video_maxi_clk>;

		clock-names = "core_clk", "iface_clk",

			      "bus_clk", "maxi_clk";

		qcom,proxy-clock-names = "core_clk", "iface_clk",
@@ -1507,7 +1507,7 @@ 


&gdsc_bimc_smmu {

	clock-names = "bus_clk";

	clocks = <&clock_mmss clk_bimc_smmu_axi_clk>;

	clocks = <&clock_mmss clk_mmss_bimc_smmu_axi_clk>;

	status = "ok";

};
@@ -1521,59 +1521,59 @@ 


&gdsc_venus {

	clock-names = "bus_clk", "maxi_clk", "core_clk";

	clocks = <&clock_mmss clk_video_axi_clk>,

		 <&clock_mmss clk_video_maxi_clk>,

		 <&clock_mmss clk_video_core_clk>;

	clocks = <&clock_mmss clk_mmss_video_axi_clk>,

		 <&clock_mmss clk_mmss_video_maxi_clk>,

		 <&clock_mmss clk_mmss_video_core_clk>;

	status = "ok";

};



&gdsc_venus_core0 {

	clock-names = "core0_clk";

	clocks = <&clock_mmss clk_video_subcore0_clk>;

	clocks = <&clock_mmss clk_mmss_video_subcore0_clk>;

	status = "ok";

};



&gdsc_venus_core1 {

	clock-names = "core1_clk";

	clocks = <&clock_mmss clk_video_subcore1_clk>;

	clocks = <&clock_mmss clk_mmss_video_subcore1_clk>;

	status = "ok";

};



&gdsc_camss_top {

	clock-names = "bus_clk", "vfe_axi";

	clocks = <&clock_mmss clk_camss_cpp_axi_clk>,

		 <&clock_mmss clk_camss_vfe_vbif_axi_clk>;

	clocks = <&clock_mmss clk_mmss_camss_cpp_axi_clk>,

		 <&clock_mmss clk_mmss_camss_vfe_vbif_axi_clk>;

	status = "ok";

};



&gdsc_vfe0 {

	clock-names = "core0_clk" , "core0_stream_clk";

	clocks = <&clock_mmss clk_camss_vfe0_clk>,

		 <&clock_mmss clk_camss_vfe0_stream_clk>;

	clocks = <&clock_mmss clk_mmss_camss_vfe0_clk>,

		 <&clock_mmss clk_mmss_camss_vfe0_stream_clk>;

	parent-supply = <&gdsc_camss_top>;

	status = "ok";

};



&gdsc_vfe1 {

	clock-names = "core1_clk" , "core1_stream_clk";

	clocks = <&clock_mmss clk_camss_vfe1_clk>,

		 <&clock_mmss clk_camss_vfe1_stream_clk>;

	clocks = <&clock_mmss clk_mmss_camss_vfe1_clk>,

		 <&clock_mmss clk_mmss_camss_vfe1_stream_clk>;

	parent-supply = <&gdsc_camss_top>;

	status = "ok";

};



&gdsc_cpp {

	clock-names = "core_clk";

	clocks = <&clock_mmss clk_camss_cpp_clk>;

	clocks = <&clock_mmss clk_mmss_camss_cpp_clk>;

	parent-supply = <&gdsc_camss_top>;

	status = "ok";

};



&gdsc_mdss {

	clock-names = "bus_clk", "core_clk", "root_clk";

	clocks = <&clock_mmss clk_mdss_axi_clk>,

		 <&clock_mmss clk_mdss_mdp_clk>,

		 <&clock_mmss clk_mdss_rot_clk>;

	clocks = <&clock_mmss clk_mmss_mdss_axi_clk>,

		 <&clock_mmss clk_mmss_mdss_mdp_clk>,

		 <&clock_mmss clk_mmss_mdss_rot_clk>;

	status = "ok";

};