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Commit d7b4394e authored by Shubhrajyoti D's avatar Shubhrajyoti D Committed by Mark Brown
Browse files

spi: omap2-mcspi: Cleanup the omap2_mcspi_txrx_dma function 



Currently in omap2_mcspi_txrx_dma the tx and the rx support is
interleaved. Make the rx related code in omap2_mcspi_rx_dma
and the tx related code omap2_mcspi_tx_dma and call the functions.

While at it remove the braces in the if statements which has only
one line.
Also fix ["foo * bar" to "foo *bar"] warn for the rx and tx variables.

Only a cleanup no functional change.

Signed-off-by: default avatarShubhrajyoti D <shubhrajyoti@ti.com>
Tested-by: default avatarFelipe Balbi <balbi@ti.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent ac2cb30b

drivers/spi/spi-omap2-mcspi.c

+144 −112
Original line number Diff line number Diff line
@@ -315,49 +315,27 @@ static void omap2_mcspi_tx_callback(void *data) 
	omap2_mcspi_set_dma_req(spi, 0, 0);

}



static unsigned

omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)

static void omap2_mcspi_tx_dma(struct spi_device *spi,

				struct spi_transfer *xfer,

				struct dma_slave_config cfg)

{

	struct omap2_mcspi	*mcspi;

	struct omap2_mcspi_cs	*cs = spi->controller_state;

	struct omap2_mcspi_dma  *mcspi_dma;

	unsigned int		count;

	int			word_len, element_count;

	int			elements = 0;

	u32			l;

	u8			* rx;

	const u8		* tx;

	void __iomem		*chstat_reg;

	struct dma_slave_config	cfg;

	enum dma_slave_buswidth width;

	unsigned es;

	struct omap2_mcspi_cs	*cs = spi->controller_state;



	mcspi = spi_master_get_devdata(spi->master);

	mcspi_dma = &mcspi->dma_channels[spi->chip_select];

	l = mcspi_cached_chconf0(spi);

	count = xfer->len;



	rx = xfer->rx_buf;

	tx = xfer->tx_buf;

	chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;



	if (cs->word_len <= 8) {

		width = DMA_SLAVE_BUSWIDTH_1_BYTE;

		es = 1;

	} else if (cs->word_len <= 16) {

		width = DMA_SLAVE_BUSWIDTH_2_BYTES;

		es = 2;

	} else {

		width = DMA_SLAVE_BUSWIDTH_4_BYTES;

		es = 4;

	}



	memset(&cfg, 0, sizeof(cfg));

	cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;

	cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;

	cfg.src_addr_width = width;

	cfg.dst_addr_width = width;

	cfg.src_maxburst = 1;

	cfg.dst_maxburst = 1;



	if (xfer->tx_buf && mcspi_dma->dma_tx) {

	if (mcspi_dma->dma_tx) {

		struct dma_async_tx_descriptor *tx;

		struct scatterlist sg;
@@ -377,8 +355,50 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) 
			/* FIXME: fall back to PIO? */

		}

	}

	dma_async_issue_pending(mcspi_dma->dma_tx);

	omap2_mcspi_set_dma_req(spi, 0, 1);



	wait_for_completion(&mcspi_dma->dma_tx_completion);

	dma_unmap_single(mcspi->dev, xfer->tx_dma, count,

			 DMA_TO_DEVICE);



	/* for TX_ONLY mode, be sure all words have shifted out */

	if (rx == NULL) {

		if (mcspi_wait_for_reg_bit(chstat_reg,

					OMAP2_MCSPI_CHSTAT_TXS) < 0)

			dev_err(&spi->dev, "TXS timed out\n");

		else if (mcspi_wait_for_reg_bit(chstat_reg,

					OMAP2_MCSPI_CHSTAT_EOT) < 0)

			dev_err(&spi->dev, "EOT timed out\n");

	}

}



static unsigned

omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,

				struct dma_slave_config cfg,

				unsigned es)

{

	struct omap2_mcspi	*mcspi;

	struct omap2_mcspi_dma  *mcspi_dma;

	unsigned int		count;

	u32			l;

	int			elements = 0;

	int			word_len, element_count;

	struct omap2_mcspi_cs	*cs = spi->controller_state;

	mcspi = spi_master_get_devdata(spi->master);

	mcspi_dma = &mcspi->dma_channels[spi->chip_select];

	count = xfer->len;

	word_len = cs->word_len;

	l = mcspi_cached_chconf0(spi);



	if (word_len <= 8)

		element_count = count;

	else if (word_len <= 16)

		element_count = count >> 1;

	else /* word_len <= 32 */

		element_count = count >> 2;



	if (xfer->rx_buf && mcspi_dma->dma_rx) {

	if (mcspi_dma->dma_rx) {

		struct dma_async_tx_descriptor *tx;

		struct scatterlist sg;

		size_t len = xfer->len - es;
@@ -393,7 +413,8 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) 
		sg_dma_len(&sg) = len;



		tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,

			DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

				DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |

				DMA_CTRL_ACK);

		if (tx) {

			tx->callback = omap2_mcspi_rx_callback;

			tx->callback_param = spi;
@@ -403,47 +424,9 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) 
		}

	}



	count = xfer->len;

	word_len = cs->word_len;



	rx = xfer->rx_buf;

	tx = xfer->tx_buf;



	if (word_len <= 8) {

		element_count = count;

	} else if (word_len <= 16) {

		element_count = count >> 1;

	} else /* word_len <= 32 */ {

		element_count = count >> 2;

	}



	if (tx != NULL) {

		dma_async_issue_pending(mcspi_dma->dma_tx);

		omap2_mcspi_set_dma_req(spi, 0, 1);

	}



	if (rx != NULL) {

	dma_async_issue_pending(mcspi_dma->dma_rx);

	omap2_mcspi_set_dma_req(spi, 1, 1);

	}



	if (tx != NULL) {

		wait_for_completion(&mcspi_dma->dma_tx_completion);

		dma_unmap_single(mcspi->dev, xfer->tx_dma, count,

				 DMA_TO_DEVICE);



		/* for TX_ONLY mode, be sure all words have shifted out */

		if (rx == NULL) {

			if (mcspi_wait_for_reg_bit(chstat_reg,

						OMAP2_MCSPI_CHSTAT_TXS) < 0)

				dev_err(&spi->dev, "TXS timed out\n");

			else if (mcspi_wait_for_reg_bit(chstat_reg,

						OMAP2_MCSPI_CHSTAT_EOT) < 0)

				dev_err(&spi->dev, "EOT timed out\n");

		}

	}



	if (rx != NULL) {

	wait_for_completion(&mcspi_dma->dma_rx_completion);

	dma_unmap_single(mcspi->dev, xfer->rx_dma, count,

			 DMA_FROM_DEVICE);
@@ -466,8 +449,7 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) 
			else /* word_len <= 32 */

				((u32 *)xfer->rx_buf)[elements++] = w;

		} else {

				dev_err(&spi->dev,

					"DMA RX penultimate word empty");

			dev_err(&spi->dev, "DMA RX penultimate word empty");

			count -= (word_len <= 8)  ? 2 :

				(word_len <= 16) ? 4 :

				/* word_len <= 32 */ 8;
@@ -475,7 +457,6 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) 
			return count;

		}

	}



	if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)

				& OMAP2_MCSPI_CHSTAT_RXS)) {

		u32 w;
@@ -494,7 +475,58 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) 
		       /* word_len <= 32 */ 4;

	}

	omap2_mcspi_set_enable(spi, 1);

	return count;

}



static unsigned

omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)

{

	struct omap2_mcspi	*mcspi;

	struct omap2_mcspi_cs	*cs = spi->controller_state;

	struct omap2_mcspi_dma  *mcspi_dma;

	unsigned int		count;

	u32			l;

	u8			*rx;

	const u8		*tx;

	struct dma_slave_config	cfg;

	enum dma_slave_buswidth width;

	unsigned es;



	mcspi = spi_master_get_devdata(spi->master);

	mcspi_dma = &mcspi->dma_channels[spi->chip_select];

	l = mcspi_cached_chconf0(spi);





	if (cs->word_len <= 8) {

		width = DMA_SLAVE_BUSWIDTH_1_BYTE;

		es = 1;

	} else if (cs->word_len <= 16) {

		width = DMA_SLAVE_BUSWIDTH_2_BYTES;

		es = 2;

	} else {

		width = DMA_SLAVE_BUSWIDTH_4_BYTES;

		es = 4;

	}



	memset(&cfg, 0, sizeof(cfg));

	cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;

	cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;

	cfg.src_addr_width = width;

	cfg.dst_addr_width = width;

	cfg.src_maxburst = 1;

	cfg.dst_maxburst = 1;



	rx = xfer->rx_buf;

	tx = xfer->tx_buf;



	count = xfer->len;



	if (tx != NULL)

		omap2_mcspi_tx_dma(spi, xfer, cfg);



	if (rx != NULL)

		return omap2_mcspi_rx_dma(spi, xfer, cfg, es);



	return count;

}