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Commit d792b1e9 authored by Gregory CLEMENT's avatar Gregory CLEMENT Committed by Jason Cooper
Browse files

arm: mvebu: add L2 cache support 



Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
Tested-and-reviewed-by: default avatarYehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: default avatarLior Amsalem <alior@marvell.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 56580bb4

arch/arm/mach-mvebu/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ config MACH_ARMADA_370_XP 
	bool

	select ARMADA_370_XP_TIMER

	select HAVE_SMP

	select CACHE_L2X0

	select CPU_PJ4B



config MACH_ARMADA_370

arch/arm/mach-mvebu/irq-armada-370-xp.c

+4 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include <asm/mach/arch.h>

#include <asm/exception.h>

#include <asm/smp_plat.h>

#include <asm/hardware/cache-l2x0.h>



/* Interrupt Controller Registers Map */

#define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
@@ -210,4 +211,7 @@ static const struct of_device_id mpic_of_match[] __initconst = { 
void __init armada_370_xp_init_irq(void)

{

	of_irq_init(mpic_of_match);

#ifdef CONFIG_CACHE_L2X0

	l2x0_of_init(0, ~0UL);

#endif

}