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Commit d7919316 authored by Osvaldo Banuelos's avatar Osvaldo Banuelos Committed by Matt Wagantall
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ARM: gic: fix restore order of distributor registers in gic_cpu_restore() 



Similar to gic_dist_restore(), the GIC config, priority and enable
registers should be restored in that order. Fix this in gic_cpu_restore()
which currently restores the enable registers before the configuration
registers.

Change-Id: Ib75640849bef81aa87a3b110fe1bd7ea4371d659
Signed-off-by: default avatarOsvaldo Banuelos <osvaldob@codeaurora.org>
[abhimany: replace this_cpu_ptr with raw_cpu_ptr]
Signed-off-by: default avatarAbhimanyu Kapur <abhimany@codeaurora.org>
parent 073b08f7

drivers/irqchip/irq-gic.c

+5 −5
Original line number Diff line number Diff line
@@ -708,11 +708,6 @@ static void gic_cpu_restore(unsigned int gic_nr) 
	if (!dist_base || !cpu_base)

		return;



	ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);

	for (i = 0; i < DIV_ROUND_UP(32, 32); i++)

		writel_relaxed_no_log(ptr[i], dist_base +

			GIC_DIST_ENABLE_SET + i * 4);



	ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);

	for (i = 0; i < DIV_ROUND_UP(32, 16); i++)

		writel_relaxed_no_log(ptr[i], dist_base +
@@ -722,6 +717,11 @@ static void gic_cpu_restore(unsigned int gic_nr) 
		writel_relaxed_no_log(GICD_INT_DEF_PRI_X4,

					dist_base + GIC_DIST_PRI + i * 4);



	ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);

	for (i = 0; i < DIV_ROUND_UP(32, 32); i++)

		writel_relaxed_no_log(ptr[i], dist_base +

			GIC_DIST_ENABLE_SET + i * 4);



	writel_relaxed_no_log(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);

	gic_cpu_if_up();

}