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Commit d770d3e6 authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: gdsc: Add support to configure clk_dis_wait value 



The CLK_DIS_WAIT bits value may differ from the default value of 0x2.
Allow the value to be taken as input from device tree as parameter
'qcom,clk-dis-wait-val'.

Change-Id: I0a42eec47a563acf667fe6dad39fcd8314e4d590
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent f0e38cbf

Documentation/devicetree/bindings/regulator/gdsc-regulator.txt

+2 −0
Original line number Diff line number Diff line
@@ -37,6 +37,8 @@ Optional properties: 
			to be force-enabled prior to turning on the core. The

			clock-name which denotes the root clock should be

			"core_root_clk".

 - qcom,clk-dis-wait-val: Input value for CLK_DIS_WAIT controls state transition

			 delay after halting clock in the collapsible core.

 - reg-names:		Names of the bases for the above "reg" registers.

			Ex. "base", "domain_addr".

 - qcom,no-status-check-on-disable: Do not poll the status bit when GDSC

drivers/clk/msm/gdsc.c

+6 −2
Original line number Diff line number Diff line
@@ -343,7 +343,7 @@ static int gdsc_probe(struct platform_device *pdev) 
	struct regulator_init_data *init_data;

	struct resource *res;

	struct gdsc *sc;

	uint32_t regval;

	uint32_t regval, clk_dis_wait_val = CLK_DIS_WAIT_VAL;

	bool retain_mem, retain_periph, support_hw_trigger;

	int i, ret;
@@ -434,9 +434,13 @@ static int gdsc_probe(struct platform_device *pdev) 
	regval = readl_relaxed(sc->gdscr);

	regval &= ~(HW_CONTROL_MASK | SW_OVERRIDE_MASK);



	if (!of_property_read_u32(pdev->dev.of_node, "qcom,clk-dis-wait-val",

				  &clk_dis_wait_val))

		clk_dis_wait_val = clk_dis_wait_val << 12;



	/* Configure wait time between states. */

	regval &= ~(EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK);

	regval |= EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;

	regval |= EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | clk_dis_wait_val;

	writel_relaxed(regval, sc->gdscr);



	sc->no_status_check_on_disable =