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Commit d75ee3be authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: clean up some magic numbers 



Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@gmail.com>
parent 9453d621

drivers/gpu/drm/radeon/r100.c

+5 −5
Original line number Diff line number Diff line
@@ -1031,8 +1031,8 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 
	WREG32(RADEON_CP_CSQ_MODE,

	       REG_SET(RADEON_INDIRECT2_START, indirect2_start) |

	       REG_SET(RADEON_INDIRECT1_START, indirect1_start));

	WREG32(0x718, 0);

	WREG32(0x744, 0x00004D4D);

	WREG32(RADEON_CP_RB_WPTR_DELAY, 0);

	WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);

	WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);

	radeon_ring_start(rdev);

	r = radeon_ring_test(rdev);
@@ -2347,10 +2347,10 @@ void r100_vga_set_state(struct radeon_device *rdev, bool state) 


	temp = RREG32(RADEON_CONFIG_CNTL);

	if (state == false) {

		temp &= ~(1<<8);

		temp |= (1<<9);

		temp &= ~RADEON_CFG_VGA_RAM_EN;

		temp |= RADEON_CFG_VGA_IO_DIS;

	} else {

		temp &= ~(1<<9);

		temp &= ~RADEON_CFG_VGA_IO_DIS;

	}

	WREG32(RADEON_CONFIG_CNTL, temp);

}

drivers/gpu/drm/radeon/r300.c

+5 −2
Original line number Diff line number Diff line
@@ -69,6 +69,9 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 
	mb();

}



#define R300_PTE_WRITEABLE (1 << 2)

#define R300_PTE_READABLE  (1 << 3)



int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)

{

	void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
@@ -78,7 +81,7 @@ int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 
	}

	addr = (lower_32_bits(addr) >> 8) |

	       ((upper_32_bits(addr) & 0xff) << 24) |

	       0xc;

	       R300_PTE_WRITEABLE | R300_PTE_READABLE;

	/* on x86 we want this to be CPU endian, on powerpc

	 * on powerpc without HW swappers, it'll get swapped on way

	 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
@@ -135,7 +138,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev) 
	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);

	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);

	/* Clear error */

	WREG32_PCIE(0x18, 0);

	WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);

	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);

	tmp |= RADEON_PCIE_TX_GART_EN;

	tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;

drivers/gpu/drm/radeon/r420.c

+1 −1
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ void r420_pipes_init(struct radeon_device *rdev) 
		       "programming pipes. Bad things might happen.\n");

	}

	/* get max number of pipes */

	gb_pipe_select = RREG32(0x402C);

	gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);

	num_pipes = ((gb_pipe_select >> 12) & 3) + 1;



	/* SE chips have 1 pipe */

drivers/gpu/drm/radeon/r520.c

+2 −2
Original line number Diff line number Diff line
@@ -79,8 +79,8 @@ static void r520_gpu_init(struct radeon_device *rdev) 
		WREG32(0x4128, 0xFF);

	}

	r420_pipes_init(rdev);

	gb_pipe_select = RREG32(0x402C);

	tmp = RREG32(0x170C);

	gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);

	tmp = RREG32(R300_DST_PIPE_CONFIG);

	pipe_select_current = (tmp >> 2) & 3;

	tmp = (1 << pipe_select_current) |

	      (((gb_pipe_select >> 8) & 0xF) << 4);

drivers/gpu/drm/radeon/radeon_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -375,6 +375,8 @@ 
#define RADEON_CONFIG_APER_SIZE             0x0108

#define RADEON_CONFIG_BONDS                 0x00e8

#define RADEON_CONFIG_CNTL                  0x00e0

#       define RADEON_CFG_VGA_RAM_EN        (1 << 8)

#       define RADEON_CFG_VGA_IO_DIS        (1 << 9)

#       define RADEON_CFG_ATI_REV_A11       (0   << 16)

#       define RADEON_CFG_ATI_REV_A12       (1   << 16)

#       define RADEON_CFG_ATI_REV_A13       (2   << 16)