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Commit d7029e1d authored by Dinesh K Garg's avatar Dinesh K Garg
Browse files

crypto: ice: Add support of BIST



Next version of ICE HW adds support of BIST. Once ICE completes BIST,
It is available for SW to use. If BIST fails, ICE HW can't be used.

Change-Id: I2b58b58ee1ac571bb9ff041d44782e0e8d910928
Signed-off-by: default avatarDinesh K Garg <dineshg@codeaurora.org>
parent 32829884
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+31 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@
#define ICE_REV(x, y) (((x) & ICE_CORE_##y##_REV_MASK) >> ICE_CORE_##y##_REV)
#define QCOM_ICE_DEV	"ice"
#define QCOM_ICE_TYPE_NAME_LEN 8
#define QCOM_ICE_MAX_BIST_CHECK_COUNT 100

const struct qcom_ice_variant_ops qcom_ice_ops;

@@ -347,6 +348,24 @@ static void qcom_ice_optimization_enable(struct ice_device *ice_dev)
static void qcom_ice_enable(struct ice_device *ice_dev)
{
	unsigned int reg;
	int count;

	if ((ICE_REV(ice_dev->ice_hw_version, MAJOR) > 2) ||
		((ICE_REV(ice_dev->ice_hw_version, MAJOR) == 2) &&
		 (ICE_REV(ice_dev->ice_hw_version, MINOR) >= 1))) {
		for (count = 0; count < QCOM_ICE_MAX_BIST_CHECK_COUNT;
						count++) {
			reg = qcom_ice_readl(ice_dev,
						QCOM_ICE_REGS_BIST_STATUS);
			if ((reg & 0xF0000000) != 0x0)
				udelay(50);
		}
		if ((reg & 0xF0000000) != 0x0) {
			pr_err("%s: BIST validation failed for ice = %p",
					__func__, (void *)ice_dev);
			BUG();
		}
	}

	/*
	 * To enable ICE, perform following
@@ -381,6 +400,18 @@ static void qcom_ice_enable(struct ice_device *ice_dev)
	 * ICE initialization/optimization instruction
	 */
	mb();


	if ((ICE_REV(ice_dev->ice_hw_version, MAJOR) > 2) ||
		((ICE_REV(ice_dev->ice_hw_version, MAJOR) == 2) &&
		 (ICE_REV(ice_dev->ice_hw_version, MINOR) >= 1))) {
		reg = qcom_ice_readl(ice_dev, QCOM_ICE_REGS_BYPASS_STATUS);
		if ((reg & 0x8000000) != 0x0) {
			pr_err("%s: Bypass failed for ice = %p",
				__func__, (void *)ice_dev);
			BUG();
		}
	}
}

static int qcom_ice_verify_ice(struct ice_device *ice_dev)
+2 −0
Original line number Diff line number Diff line
@@ -38,6 +38,8 @@
#define QCOM_ICE_REGS_NON_SEC_IRQ_STTS		0x0040
#define QCOM_ICE_REGS_NON_SEC_IRQ_MASK		0x0044
#define QCOM_ICE_REGS_NON_SEC_IRQ_CLR		0x0048
#define QCOM_ICE_REGS_BIST_STATUS		0x0070
#define QCOM_ICE_REGS_BYPASS_STATUS		0x0074
#define QCOM_ICE_REGS_ADVANCED_CONTROL		0x1000
#define QCOM_ICE_REGS_ENDIAN_SWAP		0x1004
#define QCOM_ICE_REGS_TEST_BUS_CONTROL		0x1010