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Commit d6f0f39b authored Nov 04, 2008 by Suresh Siddha Committed by Ingo Molnar Nov 06, 2008

x86: add smp_mb() before sending INVALIDATE_TLB_VECTOR



Impact: fix rare x2apic hang

On x86, x2apic mode accesses for sending IPI's don't have serializing
semantics. If the IPI receivner refers(in lock-free fashion) to some
memory setup by the sender, the need for smp_mb() before sending the
IPI becomes critical in x2apic mode.

Add the smp_mb() in native_flush_tlb_others() before sending the IPI.

Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

parent 7db282fa

arch/x86/kernel/tlb_32.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -154,6 +154,12 @@ void native_flush_tlb_others(const cpumask_t cpumaskp, struct mm_struct mm,
		flush_mm = mm;
		flush_va = va;
		cpus_or(flush_cpumask, cpumask, flush_cpumask);

		/*
		* Make the above memory operations globally visible before
		* sending the IPI.
		*/
		smp_mb();
		/*
		* We have to send the IPI only to
		* CPUs affected.

arch/x86/kernel/tlb_64.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -182,6 +182,11 @@ void native_flush_tlb_others(const cpumask_t cpumaskp, struct mm_struct mm,
		f->flush_va = va;
		cpus_or(f->flush_cpumask, cpumask, f->flush_cpumask);

		/*
		* Make the above memory operations globally visible before
		* sending the IPI.
		*/
		smp_mb();
		/*
		* We have to send the IPI only to
		* CPUs affected.