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Commit d6c96b6e authored by Jin Li's avatar Jin Li
Browse files

drm/sde: set display h/v polarity according to panel info 



The h/v polarity should always be set from the panel configuration.
For HDMI display, it's from the EDID information. For DSI display,
it's from the panel settings in the dtsi.

CRs-Fixed: 1085021
Change-Id: I3776603d7055e69eb2c8e5003ab83bc0483ab7c8
Signed-off-by: default avatarJin Li <jinl@codeaurora.org>
parent be3a5c8b

drivers/gpu/drm/msm/dsi-staging/dsi_defs.h

+2 −2
Original line number Diff line number Diff line
@@ -198,12 +198,12 @@ enum dsi_video_traffic_mode { 
 * @h_sync_width:     HSYNC width in pixels.

 * @h_front_porch:    Horizontal fron porch in pixels.

 * @h_skew:

 * @h_sync_polarity:  Polarity of HSYNC (false is active low).

 * @h_sync_polarity:  Polarity of HSYNC (false is active high).

 * @v_active:         Active height of one frame in lines.

 * @v_back_porch:     Vertical back porch in lines.

 * @v_sync_width:     VSYNC width in lines.

 * @v_front_porch:    Vertical front porch in lines.

 * @v_sync_polarity:  Polarity of VSYNC (false is active low).

 * @v_sync_polarity:  Polarity of VSYNC (false is active high).

 * @refresh_rate:     Refresh rate in Hz.

 */

struct dsi_mode_info {

drivers/gpu/drm/msm/dsi-staging/dsi_drm.c

+8 −0
Original line number Diff line number Diff line
@@ -56,6 +56,10 @@ static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode, 
		dsi_mode->flags |= DSI_MODE_FLAG_DFPS;

	if (msm_needs_vblank_pre_modeset(drm_mode))

		dsi_mode->flags |= DSI_MODE_FLAG_VBLANK_PRE_MODESET;

	dsi_mode->timing.h_sync_polarity =

		(drm_mode->flags & DRM_MODE_FLAG_PHSYNC) ? false : true;

	dsi_mode->timing.v_sync_polarity =

		(drm_mode->flags & DRM_MODE_FLAG_PVSYNC) ? false : true;

}



static void convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
@@ -87,6 +91,10 @@ static void convert_to_drm_mode(const struct dsi_display_mode *dsi_mode, 
		drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS;

	if (dsi_mode->flags & DSI_MODE_FLAG_VBLANK_PRE_MODESET)

		drm_mode->private_flags |= MSM_MODE_FLAG_VBLANK_PRE_MODESET;

	drm_mode->flags |= (dsi_mode->timing.h_sync_polarity) ?

				DRM_MODE_FLAG_NHSYNC : DRM_MODE_FLAG_PHSYNC;

	drm_mode->flags |= (dsi_mode->timing.v_sync_polarity) ?

				DRM_MODE_FLAG_NVSYNC : DRM_MODE_FLAG_PVSYNC;



	drm_mode_set_name(drm_mode);

}

drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c

+0 −6
Original line number Diff line number Diff line
@@ -79,12 +79,6 @@ static void drm_mode_to_intf_timing_params( 
	timing->underflow_clr = 0xff;

	timing->hsync_skew = mode->hskew;



	/* DSI controller cannot handle active-low sync signals. */

	if (vid_enc->hw_intf->cap->type == INTF_DSI) {

		timing->hsync_polarity = 0;

		timing->vsync_polarity = 0;

	}



	/*

	 * For edp only:

	 * DISPLAY_V_START = (VBP * HCYCLE) + HBP

drivers/gpu/drm/msm/sde/sde_hw_intf.c

+2 −7
Original line number Diff line number Diff line
@@ -148,13 +148,8 @@ static void sde_hw_intf_setup_timing_engine(struct sde_hw_intf *ctx, 
	display_hctl = (hsync_end_x << 16) | hsync_start_x;



	den_polarity = 0;

	if (ctx->cap->type == INTF_HDMI) {

		hsync_polarity = p->yres >= 720 ? 0 : 1;

		vsync_polarity = p->yres >= 720 ? 0 : 1;

	} else {

		hsync_polarity = 0;

		vsync_polarity = 0;

	}

	hsync_polarity = p->hsync_polarity;

	vsync_polarity = p->vsync_polarity;

	polarity_ctl = (den_polarity << 2) | /*  DEN Polarity  */

		(vsync_polarity << 1) | /* VSYNC Polarity */

		(hsync_polarity << 0);  /* HSYNC Polarity */