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Commit d6a60fc1 authored by Joerg Roedel's avatar Joerg Roedel
Browse files

Merge branches 'arm/exynos', 'ppc/pamu', 'arm/smmu', 'x86/amd' and 'iommu/fixes' into next

parents 6e466452 ca19243e 634544bf ecfadb6e e644a013 3269ee0b

arch/powerpc/include/asm/device.h

+3 −0
Original line number Diff line number Diff line
@@ -28,6 +28,9 @@ struct dev_archdata { 
		void		*iommu_table_base;

	} dma_data;



#ifdef CONFIG_IOMMU_API

	void			*iommu_domain;

#endif

#ifdef CONFIG_SWIOTLB

	dma_addr_t		max_direct_dma_addr;

#endif

arch/powerpc/include/asm/fsl_pamu_stash.h

0 → 100644
+39 −0
Original line number Diff line number Diff line 
/*

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License, version 2, as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.

 *

 * Copyright (C) 2013 Freescale Semiconductor, Inc.

 *

 */



#ifndef __FSL_PAMU_STASH_H

#define __FSL_PAMU_STASH_H



/* cache stash targets */

enum pamu_stash_target {

	PAMU_ATTR_CACHE_L1 = 1,

	PAMU_ATTR_CACHE_L2,

	PAMU_ATTR_CACHE_L3,

};



/*

 * This attribute allows configuring stashig specific parameters

 * in the PAMU hardware.

 */



struct pamu_stash_attribute {

	u32 	cpu;	/* cpu number */

	u32 	cache;	/* cache to stash to: L1,L2,L3 */

};



#endif  /* __FSL_PAMU_STASH_H */

arch/powerpc/sysdev/fsl_pci.h

+5 −0
Original line number Diff line number Diff line
@@ -16,6 +16,11 @@ 


struct platform_device;





/* FSL PCI controller BRR1 register */

#define PCI_FSL_BRR1      0xbf8

#define PCI_FSL_BRR1_VER 0xffff



#define PCIE_LTSSM	0x0404		/* PCIE Link Training and Status */

#define PCIE_LTSSM_L0	0x16		/* L0 state */

#define PCIE_IP_REV_2_2		0x02080202 /* PCIE IP block version Rev2.2 */

drivers/iommu/Kconfig

+10 −0
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@@ -17,6 +17,16 @@ config OF_IOMMU 
       def_bool y

       depends on OF



config FSL_PAMU

	bool "Freescale IOMMU support"

	depends on PPC_E500MC

	select IOMMU_API

	select GENERIC_ALLOCATOR

	help

	  Freescale PAMU support. PAMU is the IOMMU present on Freescale QorIQ platforms.

	  PAMU can authorize memory access, remap the memory address, and remap I/O

	  transaction types.



# MSM IOMMU support

config MSM_IOMMU

	bool "MSM IOMMU Support"

drivers/iommu/Makefile

+1 −0
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@@ -16,3 +16,4 @@ obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o 
obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o

obj-$(CONFIG_SHMOBILE_IOMMU) += shmobile-iommu.o

obj-$(CONFIG_SHMOBILE_IPMMU) += shmobile-ipmmu.o

obj-$(CONFIG_FSL_PAMU) += fsl_pamu.o fsl_pamu_domain.o