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Commit d6800f6e authored by Mayank Rana's avatar Mayank Rana Committed by Hemant Kumar
Browse files

ARM: dts: mdm: Add cfg_ahb_clk reference with USB3 for mdm platforms 



cfg_ahb_clk reference is required with USB controller driver to access
AHB2PHY register. Hence add cfg_ahb_clk reference with USB3 device node
for mdm9640, and mdmcalifornium.

Change-Id: Ie556e142fa9b464b257408c7afc8257fe46c4e66
Signed-off-by: default avatarMayank Rana <mrana@codeaurora.org>
parent f81d0b1f

arch/arm/boot/dts/qcom/mdm9640.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -644,10 +644,11 @@ 
			 <&clock_gcc clk_gcc_usb30_mock_utmi_clk>,

			 <&clock_gcc clk_gcc_usb30_sleep_clk>,

			 <&clock_gcc clk_ln_bb_clk>,

			 <&clock_gcc clk_cxo_dwc3_clk>;

			 <&clock_gcc clk_cxo_dwc3_clk>,

			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>;



		clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",

			      "ref_clk", "xo";

			      "ref_clk", "xo", "cfg_ahb_clk";



		dwc3@8a00000 {

			compatible = "synopsys,dwc3";

arch/arm/boot/dts/qcom/mdmcalifornium.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -559,10 +559,11 @@ 
			 <&clock_gcc clk_gcc_usb30_mock_utmi_clk>,

			 <&clock_gcc clk_gcc_usb30_sleep_clk>,

			 <&clock_gcc clk_ln_bb_clk>,

			 <&clock_gcc clk_cxo_dwc3_clk>;

			 <&clock_gcc clk_cxo_dwc3_clk>,

			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>;



		clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",

			      "ref_clk", "xo";

			      "ref_clk", "xo", "cfg_ahb_clk";



		dwc3@8a00000 {

			compatible = "snps,dwc3";