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Commit d67d92c0 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nv50-/disp: add method descriptions for debugging 



Lists of known methods for the DMA channel classes, and mappings to
their priv register addresses (where known).

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 117e1633

drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

+263 −0
Original line number Diff line number Diff line
@@ -226,6 +226,177 @@ nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend) 
 * EVO master channel object

 ******************************************************************************/



static void

nv50_disp_mthd_list(struct nv50_disp_priv *priv, int debug, u32 base, int c,

		    const struct nv50_disp_mthd_list *list, int inst)

{

	struct nouveau_object *disp = nv_object(priv);

	int i;



	for (i = 0; list->data[i].mthd; i++) {

		if (list->data[i].addr) {

			u32 next = nv_rd32(priv, list->data[i].addr + base + 0);

			u32 prev = nv_rd32(priv, list->data[i].addr + base + c);

			u32 mthd = list->data[i].mthd + (list->mthd * inst);

			const char *name = list->data[i].name;

			char mods[16];



			if (prev != next)

				snprintf(mods, sizeof(mods), "-> 0x%08x", next);

			else

				snprintf(mods, sizeof(mods), "%13c", ' ');



			nv_printk_(disp, debug, "\t0x%04x: 0x%08x %s%s%s\n",

				   mthd, prev, mods, name ? " // " : "",

				   name ? name : "");

		}

	}

}



void

nv50_disp_mthd_chan(struct nv50_disp_priv *priv, int debug, int head,

		    const struct nv50_disp_mthd_chan *chan)

{

	struct nouveau_object *disp = nv_object(priv);

	const struct nv50_disp_impl *impl = (void *)disp->oclass;

	const struct nv50_disp_mthd_list *list;

	int i, j;



	if (debug > nv_subdev(priv)->debug)

		return;



	for (i = 0; (list = chan->data[i].mthd) != NULL; i++) {

		u32 base = head * chan->addr;

		for (j = 0; j < chan->data[i].nr; j++, base += list->addr) {

			const char *cname = chan->name;

			const char *sname = "";

			char cname_[16], sname_[16];



			if (chan->addr) {

				snprintf(cname_, sizeof(cname_), "%s %d",

					 chan->name, head);

				cname = cname_;

			}



			if (chan->data[i].nr > 1) {

				snprintf(sname_, sizeof(sname_), " - %s %d",

					 chan->data[i].name, j);

				sname = sname_;

			}



			nv_printk_(disp, debug, "%s%s:\n", cname, sname);

			nv50_disp_mthd_list(priv, debug, base, impl->mthd.prev,

					    list, j);

		}

	}

}



const struct nv50_disp_mthd_list

nv50_disp_mast_mthd_base = {

	.mthd = 0x0000,

	.addr = 0x000000,

	.data = {

		{ 0x0080, 0x000000 },

		{ 0x0084, 0x610bb8 },

		{ 0x0088, 0x610b9c },

		{ 0x008c, 0x000000 },

		{}

	}

};



static const struct nv50_disp_mthd_list

nv50_disp_mast_mthd_dac = {

	.mthd = 0x0080,

	.addr = 0x000008,

	.data = {

		{ 0x0400, 0x610b58 },

		{ 0x0404, 0x610bdc },

		{ 0x0420, 0x610828 },

		{}

	}

};



const struct nv50_disp_mthd_list

nv50_disp_mast_mthd_sor = {

	.mthd = 0x0040,

	.addr = 0x000008,

	.data = {

		{ 0x0600, 0x610b70 },

		{}

	}

};



const struct nv50_disp_mthd_list

nv50_disp_mast_mthd_pior = {

	.mthd = 0x0040,

	.addr = 0x000008,

	.data = {

		{ 0x0700, 0x610b80 },

		{}

	}

};



static const struct nv50_disp_mthd_list

nv50_disp_mast_mthd_head = {

	.mthd = 0x0400,

	.addr = 0x000540,

	.data = {

		{ 0x0800, 0x610ad8 },

		{ 0x0804, 0x610ad0 },

		{ 0x0808, 0x610a48 },

		{ 0x080c, 0x610a78 },

		{ 0x0810, 0x610ac0 },

		{ 0x0814, 0x610af8 },

		{ 0x0818, 0x610b00 },

		{ 0x081c, 0x610ae8 },

		{ 0x0820, 0x610af0 },

		{ 0x0824, 0x610b08 },

		{ 0x0828, 0x610b10 },

		{ 0x082c, 0x610a68 },

		{ 0x0830, 0x610a60 },

		{ 0x0834, 0x000000 },

		{ 0x0838, 0x610a40 },

		{ 0x0840, 0x610a24 },

		{ 0x0844, 0x610a2c },

		{ 0x0848, 0x610aa8 },

		{ 0x084c, 0x610ab0 },

		{ 0x0860, 0x610a84 },

		{ 0x0864, 0x610a90 },

		{ 0x0868, 0x610b18 },

		{ 0x086c, 0x610b20 },

		{ 0x0870, 0x610ac8 },

		{ 0x0874, 0x610a38 },

		{ 0x0880, 0x610a58 },

		{ 0x0884, 0x610a9c },

		{ 0x08a0, 0x610a70 },

		{ 0x08a4, 0x610a50 },

		{ 0x08a8, 0x610ae0 },

		{ 0x08c0, 0x610b28 },

		{ 0x08c4, 0x610b30 },

		{ 0x08c8, 0x610b40 },

		{ 0x08d4, 0x610b38 },

		{ 0x08d8, 0x610b48 },

		{ 0x08dc, 0x610b50 },

		{ 0x0900, 0x610a18 },

		{ 0x0904, 0x610ab8 },

		{}

	}

};



static const struct nv50_disp_mthd_chan

nv50_disp_mast_mthd_chan = {

	.name = "Core",

	.addr = 0x000000,

	.data = {

		{ "Global", 1, &nv50_disp_mast_mthd_base },

		{    "DAC", 3, &nv50_disp_mast_mthd_dac  },

		{    "SOR", 2, &nv50_disp_mast_mthd_sor  },

		{   "PIOR", 3, &nv50_disp_mast_mthd_pior },

		{   "HEAD", 2, &nv50_disp_mast_mthd_head },

		{}

	}

};



static int

nv50_disp_mast_ctor(struct nouveau_object *parent,

		    struct nouveau_object *engine,
@@ -322,6 +493,56 @@ nv50_disp_mast_ofuncs = { 
 * EVO sync channel objects

 ******************************************************************************/



static const struct nv50_disp_mthd_list

nv50_disp_sync_mthd_base = {

	.mthd = 0x0000,

	.addr = 0x000000,

	.data = {

		{ 0x0080, 0x000000 },

		{ 0x0084, 0x0008c4 },

		{ 0x0088, 0x0008d0 },

		{ 0x008c, 0x0008dc },

		{ 0x0090, 0x0008e4 },

		{ 0x0094, 0x610884 },

		{ 0x00a0, 0x6108a0 },

		{ 0x00a4, 0x610878 },

		{ 0x00c0, 0x61086c },

		{ 0x00e0, 0x610858 },

		{ 0x00e4, 0x610860 },

		{ 0x00e8, 0x6108ac },

		{ 0x00ec, 0x6108b4 },

		{ 0x0100, 0x610894 },

		{ 0x0110, 0x6108bc },

		{ 0x0114, 0x61088c },

		{}

	}

};



const struct nv50_disp_mthd_list

nv50_disp_sync_mthd_image = {

	.mthd = 0x0400,

	.addr = 0x000000,

	.data = {

		{ 0x0800, 0x6108f0 },

		{ 0x0804, 0x6108fc },

		{ 0x0808, 0x61090c },

		{ 0x080c, 0x610914 },

		{ 0x0810, 0x610904 },

		{}

	}

};



static const struct nv50_disp_mthd_chan

nv50_disp_sync_mthd_chan = {

	.name = "Base",

	.addr = 0x000540,

	.data = {

		{ "Global", 1, &nv50_disp_sync_mthd_base },

		{  "Image", 2, &nv50_disp_sync_mthd_image },

		{}

	}

};



static int

nv50_disp_sync_ctor(struct nouveau_object *parent,

		    struct nouveau_object *engine,
@@ -361,6 +582,44 @@ nv50_disp_sync_ofuncs = { 
 * EVO overlay channel objects

 ******************************************************************************/



const struct nv50_disp_mthd_list

nv50_disp_ovly_mthd_base = {

	.mthd = 0x0000,

	.addr = 0x000000,

	.data = {

		{ 0x0080, 0x000000 },

		{ 0x0084, 0x0009a0 },

		{ 0x0088, 0x0009c0 },

		{ 0x008c, 0x0009c8 },

		{ 0x0090, 0x6109b4 },

		{ 0x0094, 0x610970 },

		{ 0x00a0, 0x610998 },

		{ 0x00a4, 0x610964 },

		{ 0x00c0, 0x610958 },

		{ 0x00e0, 0x6109a8 },

		{ 0x00e4, 0x6109d0 },

		{ 0x00e8, 0x6109d8 },

		{ 0x0100, 0x61094c },

		{ 0x0104, 0x610984 },

		{ 0x0108, 0x61098c },

		{ 0x0800, 0x6109f8 },

		{ 0x0808, 0x610a08 },

		{ 0x080c, 0x610a10 },

		{ 0x0810, 0x610a00 },

		{}

	}

};



static const struct nv50_disp_mthd_chan

nv50_disp_ovly_mthd_chan = {

	.name = "Overlay",

	.addr = 0x000540,

	.data = {

		{ "Global", 1, &nv50_disp_ovly_mthd_base },

		{}

	}

};



static int

nv50_disp_ovly_ctor(struct nouveau_object *parent,

		    struct nouveau_object *engine,
@@ -1376,4 +1635,8 @@ nv50_disp_oclass = &(struct nv50_disp_impl) { 
		.init = _nouveau_disp_init,

		.fini = _nouveau_disp_fini,

	},

	.mthd.core = &nv50_disp_mast_mthd_chan,

	.mthd.base = &nv50_disp_sync_mthd_chan,

	.mthd.ovly = &nv50_disp_ovly_mthd_chan,

	.mthd.prev = 0x000004,

}.base.base;

drivers/gpu/drm/nouveau/core/engine/disp/nv50.h

+48 −0
Original line number Diff line number Diff line
@@ -14,6 +14,12 @@ 


struct nv50_disp_impl {

	struct nouveau_disp_impl base;

	struct {

		const struct nv50_disp_mthd_chan *core;

		const struct nv50_disp_mthd_chan *base;

		const struct nv50_disp_mthd_chan *ovly;

		int prev;

	} mthd;

};



struct nv50_disp_priv {
@@ -128,21 +134,60 @@ struct nv50_disp_pioc { 
	struct nv50_disp_chan base;

};



struct nv50_disp_mthd_list {

	u32 mthd;

	u32 addr;

	struct {

		u32 mthd;

		u32 addr;

		const char *name;

	} data[];

};



struct nv50_disp_mthd_chan {

	const char *name;

	u32 addr;

	struct {

		const char *name;

		int nr;

		const struct nv50_disp_mthd_list *mthd;

	} data[];

};



extern struct nouveau_ofuncs nv50_disp_mast_ofuncs;

extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_base;

extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_sor;

extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_pior;

extern struct nouveau_ofuncs nv50_disp_sync_ofuncs;

extern const struct nv50_disp_mthd_list nv50_disp_sync_mthd_image;

extern struct nouveau_ofuncs nv50_disp_ovly_ofuncs;

extern const struct nv50_disp_mthd_list nv50_disp_ovly_mthd_base;

extern struct nouveau_ofuncs nv50_disp_oimm_ofuncs;

extern struct nouveau_ofuncs nv50_disp_curs_ofuncs;

extern struct nouveau_ofuncs nv50_disp_base_ofuncs;

extern struct nouveau_oclass nv50_disp_cclass;

void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head,

			 const struct nv50_disp_mthd_chan *);

void nv50_disp_intr_supervisor(struct work_struct *);

void nv50_disp_intr(struct nouveau_subdev *);



extern const struct nv50_disp_mthd_chan nv84_disp_mast_mthd_chan;

extern const struct nv50_disp_mthd_list nv84_disp_mast_mthd_dac;

extern const struct nv50_disp_mthd_list nv84_disp_mast_mthd_head;

extern const struct nv50_disp_mthd_chan nv84_disp_sync_mthd_chan;

extern const struct nv50_disp_mthd_chan nv84_disp_ovly_mthd_chan;

extern struct nouveau_omthds nv84_disp_base_omthds[];



extern const struct nv50_disp_mthd_chan nv94_disp_mast_mthd_chan;



extern struct nouveau_ofuncs nvd0_disp_mast_ofuncs;

extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_base;

extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_dac;

extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_sor;

extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_pior;

extern struct nouveau_ofuncs nvd0_disp_sync_ofuncs;

extern struct nouveau_ofuncs nvd0_disp_ovly_ofuncs;

extern const struct nv50_disp_mthd_chan nvd0_disp_sync_mthd_chan;

extern struct nouveau_ofuncs nvd0_disp_oimm_ofuncs;

extern struct nouveau_ofuncs nvd0_disp_curs_ofuncs;

extern struct nouveau_omthds nvd0_disp_base_omthds[];
@@ -151,4 +196,7 @@ extern struct nouveau_oclass nvd0_disp_cclass; 
void nvd0_disp_intr_supervisor(struct work_struct *);

void nvd0_disp_intr(struct nouveau_subdev *);



extern const struct nv50_disp_mthd_chan nve0_disp_mast_mthd_chan;

extern const struct nv50_disp_mthd_chan nve0_disp_ovly_mthd_chan;



#endif

drivers/gpu/drm/nouveau/core/engine/disp/nv84.c

+173 −0
Original line number Diff line number Diff line
@@ -29,6 +29,175 @@ 


#include "nv50.h"



/*******************************************************************************

 * EVO master channel object

 ******************************************************************************/



const struct nv50_disp_mthd_list

nv84_disp_mast_mthd_dac = {

	.mthd = 0x0080,

	.addr = 0x000008,

	.data = {

		{ 0x0400, 0x610b58 },

		{ 0x0404, 0x610bdc },

		{ 0x0420, 0x610bc4 },

		{}

	}

};



const struct nv50_disp_mthd_list

nv84_disp_mast_mthd_head = {

	.mthd = 0x0400,

	.addr = 0x000540,

	.data = {

		{ 0x0800, 0x610ad8 },

		{ 0x0804, 0x610ad0 },

		{ 0x0808, 0x610a48 },

		{ 0x080c, 0x610a78 },

		{ 0x0810, 0x610ac0 },

		{ 0x0814, 0x610af8 },

		{ 0x0818, 0x610b00 },

		{ 0x081c, 0x610ae8 },

		{ 0x0820, 0x610af0 },

		{ 0x0824, 0x610b08 },

		{ 0x0828, 0x610b10 },

		{ 0x082c, 0x610a68 },

		{ 0x0830, 0x610a60 },

		{ 0x0834, 0x000000 },

		{ 0x0838, 0x610a40 },

		{ 0x0840, 0x610a24 },

		{ 0x0844, 0x610a2c },

		{ 0x0848, 0x610aa8 },

		{ 0x084c, 0x610ab0 },

		{ 0x085c, 0x610c5c },

		{ 0x0860, 0x610a84 },

		{ 0x0864, 0x610a90 },

		{ 0x0868, 0x610b18 },

		{ 0x086c, 0x610b20 },

		{ 0x0870, 0x610ac8 },

		{ 0x0874, 0x610a38 },

		{ 0x0878, 0x610c50 },

		{ 0x0880, 0x610a58 },

		{ 0x0884, 0x610a9c },

		{ 0x089c, 0x610c68 },

		{ 0x08a0, 0x610a70 },

		{ 0x08a4, 0x610a50 },

		{ 0x08a8, 0x610ae0 },

		{ 0x08c0, 0x610b28 },

		{ 0x08c4, 0x610b30 },

		{ 0x08c8, 0x610b40 },

		{ 0x08d4, 0x610b38 },

		{ 0x08d8, 0x610b48 },

		{ 0x08dc, 0x610b50 },

		{ 0x0900, 0x610a18 },

		{ 0x0904, 0x610ab8 },

		{ 0x0910, 0x610c70 },

		{ 0x0914, 0x610c78 },

		{}

	}

};



const struct nv50_disp_mthd_chan

nv84_disp_mast_mthd_chan = {

	.name = "Core",

	.addr = 0x000000,

	.data = {

		{ "Global", 1, &nv50_disp_mast_mthd_base },

		{    "DAC", 3, &nv84_disp_mast_mthd_dac  },

		{    "SOR", 2, &nv50_disp_mast_mthd_sor  },

		{   "PIOR", 3, &nv50_disp_mast_mthd_pior },

		{   "HEAD", 2, &nv84_disp_mast_mthd_head },

		{}

	}

};



/*******************************************************************************

 * EVO sync channel objects

 ******************************************************************************/



static const struct nv50_disp_mthd_list

nv84_disp_sync_mthd_base = {

	.mthd = 0x0000,

	.addr = 0x000000,

	.data = {

		{ 0x0080, 0x000000 },

		{ 0x0084, 0x0008c4 },

		{ 0x0088, 0x0008d0 },

		{ 0x008c, 0x0008dc },

		{ 0x0090, 0x0008e4 },

		{ 0x0094, 0x610884 },

		{ 0x00a0, 0x6108a0 },

		{ 0x00a4, 0x610878 },

		{ 0x00c0, 0x61086c },

		{ 0x00c4, 0x610800 },

		{ 0x00c8, 0x61080c },

		{ 0x00cc, 0x610818 },

		{ 0x00e0, 0x610858 },

		{ 0x00e4, 0x610860 },

		{ 0x00e8, 0x6108ac },

		{ 0x00ec, 0x6108b4 },

		{ 0x00fc, 0x610824 },

		{ 0x0100, 0x610894 },

		{ 0x0104, 0x61082c },

		{ 0x0110, 0x6108bc },

		{ 0x0114, 0x61088c },

		{}

	}

};



const struct nv50_disp_mthd_chan

nv84_disp_sync_mthd_chan = {

	.name = "Base",

	.addr = 0x000540,

	.data = {

		{ "Global", 1, &nv84_disp_sync_mthd_base },

		{  "Image", 2, &nv50_disp_sync_mthd_image },

		{}

	}

};



/*******************************************************************************

 * EVO overlay channel objects

 ******************************************************************************/



static const struct nv50_disp_mthd_list

nv84_disp_ovly_mthd_base = {

	.mthd = 0x0000,

	.addr = 0x000000,

	.data = {

		{ 0x0080, 0x000000 },

		{ 0x0084, 0x6109a0 },

		{ 0x0088, 0x6109c0 },

		{ 0x008c, 0x6109c8 },

		{ 0x0090, 0x6109b4 },

		{ 0x0094, 0x610970 },

		{ 0x00a0, 0x610998 },

		{ 0x00a4, 0x610964 },

		{ 0x00c0, 0x610958 },

		{ 0x00e0, 0x6109a8 },

		{ 0x00e4, 0x6109d0 },

		{ 0x00e8, 0x6109d8 },

		{ 0x0100, 0x61094c },

		{ 0x0104, 0x610984 },

		{ 0x0108, 0x61098c },

		{ 0x0800, 0x6109f8 },

		{ 0x0808, 0x610a08 },

		{ 0x080c, 0x610a10 },

		{ 0x0810, 0x610a00 },

		{}

	}

};



const struct nv50_disp_mthd_chan

nv84_disp_ovly_mthd_chan = {

	.name = "Overlay",

	.addr = 0x000540,

	.data = {

		{ "Global", 1, &nv84_disp_ovly_mthd_base },

		{}

	}

};



/*******************************************************************************

 * Base display object

 ******************************************************************************/
@@ -108,4 +277,8 @@ nv84_disp_oclass = &(struct nv50_disp_impl) { 
		.init = _nouveau_disp_init,

		.fini = _nouveau_disp_fini,

	},

	.mthd.core = &nv84_disp_mast_mthd_chan,

	.mthd.base = &nv84_disp_sync_mthd_chan,

	.mthd.ovly = &nv84_disp_ovly_mthd_chan,

	.mthd.prev = 0x000004,

}.base.base;

drivers/gpu/drm/nouveau/core/engine/disp/nv94.c

+32 −0
Original line number Diff line number Diff line
@@ -29,6 +29,34 @@ 


#include "nv50.h"



/*******************************************************************************

 * EVO master channel object

 ******************************************************************************/



const struct nv50_disp_mthd_list

nv94_disp_mast_mthd_sor = {

	.mthd = 0x0040,

	.addr = 0x000008,

	.data = {

		{ 0x0600, 0x610794 },

		{}

	}

};



const struct nv50_disp_mthd_chan

nv94_disp_mast_mthd_chan = {

	.name = "Core",

	.addr = 0x000000,

	.data = {

		{ "Global", 1, &nv50_disp_mast_mthd_base },

		{    "DAC", 3, &nv84_disp_mast_mthd_dac  },

		{    "SOR", 4, &nv94_disp_mast_mthd_sor  },

		{   "PIOR", 3, &nv50_disp_mast_mthd_pior },

		{   "HEAD", 2, &nv84_disp_mast_mthd_head },

		{}

	}

};



/*******************************************************************************

 * Base display object

 ******************************************************************************/
@@ -109,4 +137,8 @@ nv94_disp_oclass = &(struct nv50_disp_impl) { 
		.init = _nouveau_disp_init,

		.fini = _nouveau_disp_fini,

	},

	.mthd.core = &nv94_disp_mast_mthd_chan,

	.mthd.base = &nv84_disp_sync_mthd_chan,

	.mthd.ovly = &nv84_disp_ovly_mthd_chan,

	.mthd.prev = 0x000004,

}.base.base;

drivers/gpu/drm/nouveau/core/engine/disp/nva0.c

+49 −0
Original line number Diff line number Diff line
@@ -29,6 +29,51 @@ 


#include "nv50.h"



/*******************************************************************************

 * EVO overlay channel objects

 ******************************************************************************/



static const struct nv50_disp_mthd_list

nva0_disp_ovly_mthd_base = {

	.mthd = 0x0000,

	.addr = 0x000000,

	.data = {

		{ 0x0080, 0x000000 },

		{ 0x0084, 0x6109a0 },

		{ 0x0088, 0x6109c0 },

		{ 0x008c, 0x6109c8 },

		{ 0x0090, 0x6109b4 },

		{ 0x0094, 0x610970 },

		{ 0x00a0, 0x610998 },

		{ 0x00a4, 0x610964 },

		{ 0x00b0, 0x610c98 },

		{ 0x00b4, 0x610ca4 },

		{ 0x00b8, 0x610cac },

		{ 0x00c0, 0x610958 },

		{ 0x00e0, 0x6109a8 },

		{ 0x00e4, 0x6109d0 },

		{ 0x00e8, 0x6109d8 },

		{ 0x0100, 0x61094c },

		{ 0x0104, 0x610984 },

		{ 0x0108, 0x61098c },

		{ 0x0800, 0x6109f8 },

		{ 0x0808, 0x610a08 },

		{ 0x080c, 0x610a10 },

		{ 0x0810, 0x610a00 },

		{}

	}

};



static const struct nv50_disp_mthd_chan

nva0_disp_ovly_mthd_chan = {

	.name = "Overlay",

	.addr = 0x000540,

	.data = {

		{ "Global", 1, &nva0_disp_ovly_mthd_base },

		{}

	}

};



/*******************************************************************************

 * Base display object

 ******************************************************************************/
@@ -94,4 +139,8 @@ nva0_disp_oclass = &(struct nv50_disp_impl) { 
		.init = _nouveau_disp_init,

		.fini = _nouveau_disp_fini,

	},

	.mthd.core = &nv84_disp_mast_mthd_chan,

	.mthd.base = &nv84_disp_sync_mthd_chan,

	.mthd.ovly = &nva0_disp_ovly_mthd_chan,

	.mthd.prev = 0x000004,

}.base.base;