Loading arch/alpha/kernel/sys_dp264.c +27 −25 Original line number Diff line number Diff line Loading @@ -98,37 +98,37 @@ tsunami_update_irq_hw(unsigned long mask) } static void dp264_enable_irq(unsigned int irq) dp264_enable_irq(struct irq_data *d) { spin_lock(&dp264_irq_lock); cached_irq_mask |= 1UL << irq; cached_irq_mask |= 1UL << d->irq; tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); } static void dp264_disable_irq(unsigned int irq) dp264_disable_irq(struct irq_data *d) { spin_lock(&dp264_irq_lock); cached_irq_mask &= ~(1UL << irq); cached_irq_mask &= ~(1UL << d->irq); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); } static void clipper_enable_irq(unsigned int irq) clipper_enable_irq(struct irq_data *d) { spin_lock(&dp264_irq_lock); cached_irq_mask |= 1UL << (irq - 16); cached_irq_mask |= 1UL << (d->irq - 16); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); } static void clipper_disable_irq(unsigned int irq) clipper_disable_irq(struct irq_data *d) { spin_lock(&dp264_irq_lock); cached_irq_mask &= ~(1UL << (irq - 16)); cached_irq_mask &= ~(1UL << (d->irq - 16)); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); } Loading @@ -149,10 +149,11 @@ cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) } static int dp264_set_affinity(unsigned int irq, const struct cpumask *affinity) dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity, bool force) { spin_lock(&dp264_irq_lock); cpu_set_irq_affinity(irq, *affinity); cpu_set_irq_affinity(d->irq, *affinity); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); Loading @@ -160,10 +161,11 @@ dp264_set_affinity(unsigned int irq, const struct cpumask *affinity) } static int clipper_set_affinity(unsigned int irq, const struct cpumask *affinity) clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity, bool force) { spin_lock(&dp264_irq_lock); cpu_set_irq_affinity(irq - 16, *affinity); cpu_set_irq_affinity(d->irq - 16, *affinity); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); Loading @@ -172,18 +174,18 @@ clipper_set_affinity(unsigned int irq, const struct cpumask *affinity) static struct irq_chip dp264_irq_type = { .name = "DP264", .unmask = dp264_enable_irq, .mask = dp264_disable_irq, .mask_ack = dp264_disable_irq, .set_affinity = dp264_set_affinity, .irq_unmask = dp264_enable_irq, .irq_mask = dp264_disable_irq, .irq_mask_ack = dp264_disable_irq, .irq_set_affinity = dp264_set_affinity, }; static struct irq_chip clipper_irq_type = { .name = "CLIPPER", .unmask = clipper_enable_irq, .mask = clipper_disable_irq, .mask_ack = clipper_disable_irq, .set_affinity = clipper_set_affinity, .irq_unmask = clipper_enable_irq, .irq_mask = clipper_disable_irq, .irq_mask_ack = clipper_disable_irq, .irq_set_affinity = clipper_set_affinity, }; static void Loading Loading @@ -268,8 +270,8 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax) { long i; for (i = imin; i <= imax; ++i) { irq_to_desc(i)->status |= IRQ_LEVEL; set_irq_chip_and_handler(i, ops, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } } Loading Loading
arch/alpha/kernel/sys_dp264.c +27 −25 Original line number Diff line number Diff line Loading @@ -98,37 +98,37 @@ tsunami_update_irq_hw(unsigned long mask) } static void dp264_enable_irq(unsigned int irq) dp264_enable_irq(struct irq_data *d) { spin_lock(&dp264_irq_lock); cached_irq_mask |= 1UL << irq; cached_irq_mask |= 1UL << d->irq; tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); } static void dp264_disable_irq(unsigned int irq) dp264_disable_irq(struct irq_data *d) { spin_lock(&dp264_irq_lock); cached_irq_mask &= ~(1UL << irq); cached_irq_mask &= ~(1UL << d->irq); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); } static void clipper_enable_irq(unsigned int irq) clipper_enable_irq(struct irq_data *d) { spin_lock(&dp264_irq_lock); cached_irq_mask |= 1UL << (irq - 16); cached_irq_mask |= 1UL << (d->irq - 16); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); } static void clipper_disable_irq(unsigned int irq) clipper_disable_irq(struct irq_data *d) { spin_lock(&dp264_irq_lock); cached_irq_mask &= ~(1UL << (irq - 16)); cached_irq_mask &= ~(1UL << (d->irq - 16)); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); } Loading @@ -149,10 +149,11 @@ cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) } static int dp264_set_affinity(unsigned int irq, const struct cpumask *affinity) dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity, bool force) { spin_lock(&dp264_irq_lock); cpu_set_irq_affinity(irq, *affinity); cpu_set_irq_affinity(d->irq, *affinity); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); Loading @@ -160,10 +161,11 @@ dp264_set_affinity(unsigned int irq, const struct cpumask *affinity) } static int clipper_set_affinity(unsigned int irq, const struct cpumask *affinity) clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity, bool force) { spin_lock(&dp264_irq_lock); cpu_set_irq_affinity(irq - 16, *affinity); cpu_set_irq_affinity(d->irq - 16, *affinity); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); Loading @@ -172,18 +174,18 @@ clipper_set_affinity(unsigned int irq, const struct cpumask *affinity) static struct irq_chip dp264_irq_type = { .name = "DP264", .unmask = dp264_enable_irq, .mask = dp264_disable_irq, .mask_ack = dp264_disable_irq, .set_affinity = dp264_set_affinity, .irq_unmask = dp264_enable_irq, .irq_mask = dp264_disable_irq, .irq_mask_ack = dp264_disable_irq, .irq_set_affinity = dp264_set_affinity, }; static struct irq_chip clipper_irq_type = { .name = "CLIPPER", .unmask = clipper_enable_irq, .mask = clipper_disable_irq, .mask_ack = clipper_disable_irq, .set_affinity = clipper_set_affinity, .irq_unmask = clipper_enable_irq, .irq_mask = clipper_disable_irq, .irq_mask_ack = clipper_disable_irq, .irq_set_affinity = clipper_set_affinity, }; static void Loading Loading @@ -268,8 +270,8 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax) { long i; for (i = imin; i <= imax; ++i) { irq_to_desc(i)->status |= IRQ_LEVEL; set_irq_chip_and_handler(i, ops, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } } Loading