Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d6748066 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (37 commits)
  MIPS: O32: Provide definition of registers ta0 .. ta3.
  MIPS: perf: Add Octeon support for hardware perf.
  MIPS: perf: Add support for 64-bit perf counters.
  MIPS: perf: Reorganize contents of perf support files.
  MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c
  MIPS: Add accessor macros for 64-bit performance counter registers.
  MIPS: Add probes for more Octeon II CPUs.
  MIPS: Add more CPU identifiers for Octeon II CPUs.
  MIPS: XLR, XLS: Add comment for smp setup
  MIPS: JZ4740: GPIO: Check correct IRQ in demux handler
  MIPS: JZ4740: GPIO: Simplify IRQ demuxer
  MIPS: JZ4740: Use generic irq chip
  MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines
  MIPS: Alchemy: kill au1xxx.h header
  MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines
  MIPS, IDE: Alchem, au1xxx-ide: Remove pb1200/db1200 header dep
  MIPS: Alchemy: Redo PCI as platform driver
  MIPS: Alchemy: more base address cleanup
  MIPS: Alchemy: rewrite USB platform setup.
  MIPS: Alchemy: abstract USB block control register access
  ...

Fix up trivial conflicts in:
	arch/mips/alchemy/devboards/db1x00/platform.c
	drivers/ide/Kconfig
	drivers/mmc/host/au1xmmc.c
	drivers/video/Kconfig
	sound/mips/Kconfig
parents f04c045f 3ba1e543

arch/mips/Kconfig

+4 −1
Original line number Diff line number Diff line
@@ -47,6 +47,8 @@ config MIPS_ALCHEMY 
	select GENERIC_GPIO

	select ARCH_WANT_OPTIONAL_GPIOLIB

	select SYS_SUPPORTS_ZBOOT

	select USB_ARCH_HAS_OHCI

	select USB_ARCH_HAS_EHCI



config AR7

	bool "Texas Instruments AR7"
@@ -206,6 +208,7 @@ config MACH_JZ4740 
	select SYS_HAS_EARLY_PRINTK

	select HAVE_PWM

	select HAVE_CLK

	select GENERIC_IRQ_CHIP



config LANTIQ

	bool "Lantiq based platforms"
@@ -2092,7 +2095,7 @@ config NODES_SHIFT 


config HW_PERF_EVENTS

	bool "Enable hardware performance counter support for perf events"

	depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && CPU_MIPS32

	depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON)

	default y

	help

	  Enable hardware performance counter support for perf events. If

arch/mips/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -226,7 +226,7 @@ LDFLAGS += -m $(ld-emul) 
ifdef CONFIG_MIPS

CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -xc /dev/null | \

	egrep -vw '__GNUC_(|MINOR_|PATCHLEVEL_)_' | \

	sed -e 's/^\#define /-D/' -e "s/ /='/" -e "s/$$/'/")

	sed -e "s/^\#define /-D'/" -e "s/ /'='/" -e "s/$$/'/")

ifdef CONFIG_64BIT

CHECKFLAGS		+= -m64

endif
@@ -295,7 +295,9 @@ endif 


install:

	$(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)

ifdef CONFIG_SYS_SUPPORTS_ZBOOT

	$(Q)install -D -m 755 vmlinuz $(INSTALL_PATH)/vmlinuz-$(KERNELRELEASE)

endif

	$(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)

	$(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)

arch/mips/alchemy/Kconfig

+15 −35
Original line number Diff line number Diff line
@@ -18,20 +18,20 @@ config MIPS_MTX1 
	bool "4G Systems MTX-1 board"

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select SOC_AU1500

	select ALCHEMY_GPIOINT_AU1000

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_HAS_EARLY_PRINTK



config MIPS_BOSPORUS

	bool "Alchemy Bosporus board"

	select SOC_AU1500

	select ALCHEMY_GPIOINT_AU1000

	select DMA_NONCOHERENT

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_HAS_EARLY_PRINTK



config MIPS_DB1000

	bool "Alchemy DB1000 board"

	select SOC_AU1000

	select ALCHEMY_GPIOINT_AU1000

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -39,14 +39,14 @@ config MIPS_DB1000 


config MIPS_DB1100

	bool "Alchemy DB1100 board"

	select SOC_AU1100

	select ALCHEMY_GPIOINT_AU1000

	select DMA_NONCOHERENT

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_HAS_EARLY_PRINTK



config MIPS_DB1200

	bool "Alchemy DB1200 board"

	select SOC_AU1200

	select ALCHEMY_GPIOINT_AU1000

	select DMA_COHERENT

	select MIPS_DISABLE_OBSOLETE_IDE

	select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -54,7 +54,7 @@ config MIPS_DB1200 


config MIPS_DB1500

	bool "Alchemy DB1500 board"

	select SOC_AU1500

	select ALCHEMY_GPIOINT_AU1000

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select MIPS_DISABLE_OBSOLETE_IDE
@@ -64,7 +64,7 @@ config MIPS_DB1500 


config MIPS_DB1550

	bool "Alchemy DB1550 board"

	select SOC_AU1550

	select ALCHEMY_GPIOINT_AU1000

	select HW_HAS_PCI

	select DMA_NONCOHERENT

	select MIPS_DISABLE_OBSOLETE_IDE
@@ -74,13 +74,13 @@ config MIPS_DB1550 
config MIPS_MIRAGE

	bool "Alchemy Mirage board"

	select DMA_NONCOHERENT

	select SOC_AU1500

	select ALCHEMY_GPIOINT_AU1000

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_HAS_EARLY_PRINTK



config MIPS_PB1000

	bool "Alchemy PB1000 board"

	select SOC_AU1000

	select ALCHEMY_GPIOINT_AU1000

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select SWAP_IO_SPACE
@@ -89,7 +89,7 @@ config MIPS_PB1000 


config MIPS_PB1100

	bool "Alchemy PB1100 board"

	select SOC_AU1100

	select ALCHEMY_GPIOINT_AU1000

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select SWAP_IO_SPACE
@@ -98,7 +98,7 @@ config MIPS_PB1100 


config MIPS_PB1200

	bool "Alchemy PB1200 board"

	select SOC_AU1200

	select ALCHEMY_GPIOINT_AU1000

	select DMA_NONCOHERENT

	select MIPS_DISABLE_OBSOLETE_IDE

	select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -106,7 +106,7 @@ config MIPS_PB1200 


config MIPS_PB1500

	bool "Alchemy PB1500 board"

	select SOC_AU1500

	select ALCHEMY_GPIOINT_AU1000

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -114,7 +114,7 @@ config MIPS_PB1500 


config MIPS_PB1550

	bool "Alchemy PB1550 board"

	select SOC_AU1550

	select ALCHEMY_GPIOINT_AU1000

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select MIPS_DISABLE_OBSOLETE_IDE
@@ -124,13 +124,13 @@ config MIPS_PB1550 
config MIPS_XXS1500

	bool "MyCable XXS1500 board"

	select DMA_NONCOHERENT

	select SOC_AU1500

	select ALCHEMY_GPIOINT_AU1000

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_HAS_EARLY_PRINTK



config MIPS_GPR

	bool "Trapeze ITS GPR board"

	select SOC_AU1550

	select ALCHEMY_GPIOINT_AU1000

	select HW_HAS_PCI

	select DMA_NONCOHERENT

	select MIPS_DISABLE_OBSOLETE_IDE
@@ -138,23 +138,3 @@ config MIPS_GPR 
	select SYS_HAS_EARLY_PRINTK



endchoice
 


config SOC_AU1000

	bool

	select ALCHEMY_GPIOINT_AU1000



config SOC_AU1100

	bool

	select ALCHEMY_GPIOINT_AU1000



config SOC_AU1500

	bool

	select ALCHEMY_GPIOINT_AU1000



config SOC_AU1550

	bool

	select ALCHEMY_GPIOINT_AU1000



config SOC_AU1200

	bool

	select ALCHEMY_GPIOINT_AU1000

arch/mips/alchemy/common/Makefile

+1 −5
Original line number Diff line number Diff line
@@ -12,9 +12,5 @@ obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o 


# optional gpiolib support

ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)

 ifeq ($(CONFIG_GPIOLIB),y)

  obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o

 obj-$(CONFIG_GPIOLIB) += gpiolib.o

endif
 
endif



obj-$(CONFIG_PCI)		+= pci.o

arch/mips/alchemy/common/dbdma.c

+91 −112
Original line number Diff line number Diff line
@@ -40,8 +40,6 @@ 
#include <asm/mach-au1x00/au1000.h>

#include <asm/mach-au1x00/au1xxx_dbdma.h>



#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)



/*

 * The Descriptor Based DMA supports up to 16 channels.

 *
@@ -62,120 +60,96 @@ static dbdma_global_t *dbdma_gptr = 
			(dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);

static int dbdma_initialized;



static dbdev_tab_t dbdev_tab[] = {

#ifdef CONFIG_SOC_AU1550

static dbdev_tab_t *dbdev_tab;



static dbdev_tab_t au1550_dbdev_tab[] __initdata = {

	/* UARTS */

	{ DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },

	{ DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },

	{ DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },

	{ DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },

	{ AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },

	{ AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN,  0, 8, 0x11100000, 0, 0 },

	{ AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },

	{ AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN,  0, 8, 0x11400000, 0, 0 },



	/* EXT DMA */

	{ DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },

	{ AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },

	{ AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },

	{ AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },

	{ AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },



	/* USB DEV */

	{ DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },

	{ DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },

	{ DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },

	{ DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },

	{ DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },

	{ DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },



	/* PSC 0 */

	{ DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },

	{ DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },



	/* PSC 1 */

	{ DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },

	{ DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },



	/* PSC 2 */

	{ DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },

	{ DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },



	/* PSC 3 */

	{ DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },

	{ DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },



	{ DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 },	/* PCI */

	{ DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 },	/* NAND */

	{ AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN,  4, 8, 0x10200000, 0, 0 },

	{ AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },

	{ AU1550_DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },

	{ AU1550_DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },

	{ AU1550_DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN,  4, 8, 0x10200010, 0, 0 },

	{ AU1550_DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN,  4, 8, 0x10200014, 0, 0 },



	/* PSCs */

	{ AU1550_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },

	{ AU1550_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN,  0, 0, 0x11a0001c, 0, 0 },

	{ AU1550_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },

	{ AU1550_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN,  0, 0, 0x11b0001c, 0, 0 },

	{ AU1550_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },

	{ AU1550_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN,  0, 0, 0x10a0001c, 0, 0 },

	{ AU1550_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },

	{ AU1550_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN,  0, 0, 0x10b0001c, 0, 0 },



	{ AU1550_DSCR_CMD0_PCI_WRITE,  0, 0, 0, 0x00000000, 0, 0 },  /* PCI */

	{ AU1550_DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */



	/* MAC 0 */

	{ DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },

	{ AU1550_DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN,  0, 0, 0x00000000, 0, 0 },

	{ AU1550_DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },



	/* MAC 1 */

	{ DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },



#endif /* CONFIG_SOC_AU1550 */

	{ AU1550_DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN,  0, 0, 0x00000000, 0, 0 },

	{ AU1550_DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },



#ifdef CONFIG_SOC_AU1200

	{ DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },

	{ DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },

	{ DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },

	{ DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },



	{ DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_ALWAYS,   DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

};



	{ DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

static dbdev_tab_t au1200_dbdev_tab[] __initdata = {

	{ AU1200_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },

	{ AU1200_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN,  0, 8, 0x11100000, 0, 0 },

	{ AU1200_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },

	{ AU1200_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN,  0, 8, 0x11200000, 0, 0 },



	{ DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },

	{ DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },

	{ DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },

	{ DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },

	{ AU1200_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },



	{ DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },

	{ DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },

	{ AU1200_DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },



	{ DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },

	{ DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },

	{ DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },

	{ AU1200_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN,  4, 8, 0x10600004, 0, 0 },

	{ AU1200_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },

	{ AU1200_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN,  4, 8, 0x10680004, 0, 0 },



	{ DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },

	{ DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },

	{ DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },

	{ AU1200_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },



	{ DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },

	{ DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },

	{ DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },

	{ DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_PSC0_TX,   DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },

	{ AU1200_DSCR_CMD0_PSC0_RX,   DEV_FLAGS_IN,  0, 16, 0x11a0001c, 0, 0 },

	{ AU1200_DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_PSC1_TX,   DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },

	{ AU1200_DSCR_CMD0_PSC1_RX,   DEV_FLAGS_IN,  0, 16, 0x11b0001c, 0, 0 },

	{ AU1200_DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },



	{ DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_CIM_RXA,  DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },

	{ AU1200_DSCR_CMD0_CIM_RXB,  DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },

	{ AU1200_DSCR_CMD0_CIM_RXC,  DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },

	{ AU1200_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },



#endif /* CONFIG_SOC_AU1200 */

	{ AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },



	{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_ALWAYS,   DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },



	/* Provide 16 user definable device types */

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

};



#define DBDEV_TAB_SIZE	ARRAY_SIZE(dbdev_tab)



/* 32 predefined plus 32 custom */

#define DBDEV_TAB_SIZE		64



static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
@@ -1028,38 +1002,43 @@ static struct syscore_ops alchemy_dbdma_syscore_ops = { 
	.resume		= alchemy_dbdma_resume,

};



static int __init au1xxx_dbdma_init(void)

static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)

{

	int irq_nr, ret;

	int ret;



	dbdev_tab = kzalloc(sizeof(dbdev_tab_t) * DBDEV_TAB_SIZE, GFP_KERNEL);

	if (!dbdev_tab)

		return -ENOMEM;



	memcpy(dbdev_tab, idtable, 32 * sizeof(dbdev_tab_t));

	for (ret = 32; ret < DBDEV_TAB_SIZE; ret++)

		dbdev_tab[ret].dev_id = ~0;



	dbdma_gptr->ddma_config = 0;

	dbdma_gptr->ddma_throttle = 0;

	dbdma_gptr->ddma_inten = 0xffff;

	au_sync();



	switch (alchemy_get_cputype()) {

	case ALCHEMY_CPU_AU1550:

		irq_nr = AU1550_DDMA_INT;

		break;

	case ALCHEMY_CPU_AU1200:

		irq_nr = AU1200_DDMA_INT;

		break;

	default:

		return -ENODEV;

	}



	ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,

			"Au1xxx dbdma", (void *)dbdma_gptr);

	ret = request_irq(irq, dbdma_interrupt, IRQF_DISABLED, "dbdma",

			  (void *)dbdma_gptr);

	if (ret)

		printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");

	else {

		dbdma_initialized = 1;

		printk(KERN_INFO "Alchemy DBDMA initialized\n");

		register_syscore_ops(&alchemy_dbdma_syscore_ops);

	}



	return ret;

}

subsys_initcall(au1xxx_dbdma_init);



#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
 
static int __init alchemy_dbdma_init(void)

{

	switch (alchemy_get_cputype()) {

	case ALCHEMY_CPU_AU1550:

		return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);

	case ALCHEMY_CPU_AU1200:

		return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);

	}

	return 0;

}

subsys_initcall(alchemy_dbdma_init);