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Commit d6186de0 authored by Jeevan Shriram's avatar Jeevan Shriram
Browse files

clk: mdss: remove configuring phy registers during pll disable 



DSI driver needs to disable pll and enable clamps before entering into
low power state. Since the PLL disable is configuring GLBL_TEST_CNTRL,
CLK_BUF PHY registers to 0, these registers are not restored after the
clamps are disabled.  This change avoids configuring these registers
during PLL disable and gets disabled during dsi off.

Change-Id: Ia577099679f23cb9d0d42417863b6b3ad3af635b
Signed-off-by: default avatarJeevan Shriram <jshriram@codeaurora.org>
parent fd854d74

drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c

+0 −16
Original line number Diff line number Diff line
@@ -295,22 +295,6 @@ static void dsi_pll_disable(struct clk *c) 


	dsi_pll_stop_8996(pll->pll_base);



	/* stop pll output */

	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_PLL_CLKBUFLR_EN, 0);

	/* stop clk */

	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_GLBL_TEST_CTRL, 0);

	/* stop digital block */

	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CTRL_0, 0x0);



	if (slave) {

		/* stop pll output */

		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_PLL_CLKBUFLR_EN, 0);

		/* stop clk */

		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_GLBL_TEST_CTRL, 0);

		/* stop digital block */

		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CTRL_0, 0x0);

	}



	mdss_pll_resource_enable(pll, false);



	pll->pll_on = false;

drivers/video/msm/mdss/mdss_dsi.c

+3 −3
Original line number Diff line number Diff line
@@ -1040,8 +1040,9 @@ static int mdss_dsi_off(struct mdss_panel_data *pdata, int power_state) 
		goto panel_power_ctrl;

	}



	mdss_dsi_clk_ctrl(ctrl_pdata, DSI_LINK_CLKS, 0);

	if (pdata->panel_info.type == MIPI_CMD_PANEL)

		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 1);

		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_CORE_CLKS, 1);



	if (!pdata->panel_info.ulps_suspend_enabled) {

		/* disable DSI controller */
@@ -1050,8 +1051,7 @@ static int mdss_dsi_off(struct mdss_panel_data *pdata, int power_state) 
		/* disable DSI phy */

		mdss_dsi_phy_disable(ctrl_pdata);

	}



	mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 0);

	mdss_dsi_clk_ctrl(ctrl_pdata, DSI_CORE_CLKS, 0);



panel_power_ctrl:

	ret = mdss_dsi_panel_power_ctrl(pdata, power_state);

drivers/video/msm/mdss/msm_mdss_io_8974.c

+6 −4
Original line number Diff line number Diff line
@@ -133,11 +133,13 @@ static void mdss_dsi_phy_shutdown(struct mdss_dsi_ctrl_pdata *ctrl) 
	}



	if (IS_MDSS_MAJOR_MINOR_SAME(ctrl->shared_data->hw_rev,

		MDSS_DSI_HW_REV_104))

		MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, ~0x1F);

	else

		MDSS_DSI_HW_REV_104)) {

		MIPI_OUTP(ctrl->phy_io.base + DSIPHY_PLL_CLKBUFLR_EN, 0);

		MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_GLBL_TEST_CTRL, 0);

		MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0);

	} else {

		MIPI_OUTP(ctrl->phy_io.base + MDSS_DSI_DSIPHY_CTRL_0, 0x000);



	}

}



/**