msm: clk: refactor DSI PLL driver for 28nm LPM PHY

The current DSI PLL driver for 28nm LPM PHY supports only DSI PLL0
which will be able to drive the DSI link clocks for single DSI
and split DSI use cases. Add the support for DSI PLL1 which is
needed to drive the DSI link clocks for a secondary DSI panel
for use cases where two independent DSI panels are involved.

Change-Id: I1a6ed14b760acf0f2cb6d131d754abcd1b507ca9
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>