Loading arch/arm/boot/dts/qcom/apq8009w-bg-wtp-v1.dts +14 −0 Original line number Diff line number Diff line Loading @@ -87,6 +87,20 @@ pinctrl-0 = <&uart_console_sleep>; }; &soc { spi@78b6000 { /* BLSP1 QUP2 */ status = "ok"; qcom,bg-spi { compatible = "qcom,bg-spi"; reg = <0>; spi-max-frequency = <19200000>; interrupt-parent = <&msm_gpio>; qcom,irq-gpio = <&msm_gpio 110 1>; }; }; }; /* Pinctrl dt nodes for interrupt and reset gpio for ITE tech controller */ &ts_int_active { mux { Loading arch/arm/boot/dts/qcom/apq8009w-bg-wtp-v2.dts +14 −0 Original line number Diff line number Diff line Loading @@ -102,3 +102,17 @@ pinctrl-names = "default"; pinctrl-0 = <&uart_console_sleep>; }; &soc { spi@78b6000 { /* BLSP1 QUP2 */ status = "ok"; qcom,bg-spi { compatible = "qcom,bg-spi"; reg = <0>; spi-max-frequency = <19200000>; interrupt-parent = <&msm_gpio>; qcom,irq-gpio = <&msm_gpio 110 1>; }; }; }; Loading
arch/arm/boot/dts/qcom/apq8009w-bg-wtp-v1.dts +14 −0 Original line number Diff line number Diff line Loading @@ -87,6 +87,20 @@ pinctrl-0 = <&uart_console_sleep>; }; &soc { spi@78b6000 { /* BLSP1 QUP2 */ status = "ok"; qcom,bg-spi { compatible = "qcom,bg-spi"; reg = <0>; spi-max-frequency = <19200000>; interrupt-parent = <&msm_gpio>; qcom,irq-gpio = <&msm_gpio 110 1>; }; }; }; /* Pinctrl dt nodes for interrupt and reset gpio for ITE tech controller */ &ts_int_active { mux { Loading
arch/arm/boot/dts/qcom/apq8009w-bg-wtp-v2.dts +14 −0 Original line number Diff line number Diff line Loading @@ -102,3 +102,17 @@ pinctrl-names = "default"; pinctrl-0 = <&uart_console_sleep>; }; &soc { spi@78b6000 { /* BLSP1 QUP2 */ status = "ok"; qcom,bg-spi { compatible = "qcom,bg-spi"; reg = <0>; spi-max-frequency = <19200000>; interrupt-parent = <&msm_gpio>; qcom,irq-gpio = <&msm_gpio 110 1>; }; }; };