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Commit d5570a72 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: POSTING_READ the new rps value 



In order to keep our cached values in sync with the hardware, we need a
posting read here.

CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent df6eedc8

drivers/gpu/drm/i915/intel_pm.c

+2 −0
Original line number Diff line number Diff line
@@ -2338,6 +2338,8 @@ void gen6_set_rps(struct drm_device *dev, u8 val) 
	 */

	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);



	POSTING_READ(GEN6_RPNSWREQ);



	dev_priv->rps.cur_delay = val;



	trace_intel_gpu_freq_change(val * 50);