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Commit d53ef114 authored by Stephen Boyd's avatar Stephen Boyd Committed by Daniel Lezcano
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Documentation: Add memory mapped ARM architected timer binding 



Add a binding for the arm architected timer hardware's memory
mapped interface. The mmio timer hardware is made up of one base
frame and a collection of up to 8 timer frames, where each of the
8 timer frames can have either one or two views. A frame
typically maps to a privilege level (user/kernel, hypervisor,
secure). The first view has full access to the registers within a
frame, while the second view can be restricted to particular
registers within a frame. Each frame must support a physical
timer. It's optional for a frame to support a virtual timer.

Cc: devicetree-discuss@lists.ozlabs.org
Cc: Marc Zyngier <Marc.Zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Rob Herring <robherring2@gmail.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
parent 1ff99ea6

Documentation/devicetree/bindings/arm/arch_timer.txt

+56 −3
Original line number Diff line number Diff line 
* ARM architected timer



ARM cores may have a per-core architected timer, which provides per-cpu timers.

ARM cores may have a per-core architected timer, which provides per-cpu timers,

or a memory mapped architected timer, which provides up to 8 frames with a

physical and optional virtual timer per frame.



The timer is attached to a GIC to deliver its per-processor interrupts.

The per-core architected timer is attached to a GIC to deliver its

per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC

to deliver its interrupts via SPIs.



** Timer node properties:

** CP15 Timer node properties:



- compatible : Should at least contain one of

	"arm,armv7-timer"
@@ -26,3 +30,52 @@ Example: 
			     <1 10 0xf08>;

		clock-frequency = <100000000>;

	};



** Memory mapped timer node properties:



- compatible : Should at least contain "arm,armv7-timer-mem".



- clock-frequency : The frequency of the main counter, in Hz. Optional.



- reg : The control frame base address.



Note that #address-cells, #size-cells, and ranges shall be present to ensure

the CPU can address a frame's registers.



A timer node has up to 8 frame sub-nodes, each with the following properties:



- frame-number: 0 to 7.



- interrupts : Interrupt list for physical and virtual timers in that order.

  The virtual timer interrupt is optional.



- reg : The first and second view base addresses in that order. The second view

  base address is optional.



- status : "disabled" indicates the frame is not available for use. Optional.



Example:



	timer@f0000000 {

		compatible = "arm,armv7-timer-mem";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		reg = <0xf0000000 0x1000>;

		clock-frequency = <50000000>;



		frame@f0001000 {

			frame-number = <0>

			interrupts = <0 13 0x8>,

				     <0 14 0x8>;

			reg = <0xf0001000 0x1000>,

			      <0xf0002000 0x1000>;

		};



		frame@f0003000 {

			frame-number = <1>

			interrupts = <0 15 0x8>;

			reg = <0xf0003000 0x1000>;

			status = "disabled";

		};

	};