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Commit d4e292e7 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: msm: clock-8996: Load OPP tables from generic clock driver 



Use the generic clock support to load OPP tables for the
graphics clocks on msm8996.

Change-Id: I5a08652295e8d3d2e2ae466c7f11cadd12cc668a
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 61c561fd

arch/arm/boot/dts/qcom/msm8996-v2.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 


&clock_gpu {

	compatible = "qcom,gpucc-8996-v2";

	qcom,gfx3d_clk_src_v2-opp-handle = <&msm_gpu>;

	qcom,gfxfreq-corner-v2 =

		<	   0  0  0 >,

		<  125000000  3  4 >,

arch/arm/boot/dts/qcom/msm8996-v3.0.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ 


&clock_gpu {

	compatible = "qcom,gpucc-8996-v3.0";

	qcom,gfx3d_clk_src_v2-opp-handle = <&msm_gpu>;

	qcom,gfxfreq-corner-v2 =

		<	   0  0  0 >,

		<  133000000  3  4 >,

arch/arm/boot/dts/qcom/msm8996-v3.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 


&clock_gpu {

	compatible = "qcom,gpucc-8996-v3";

	qcom,gfx3d_clk_src_v2-opp-handle = <&msm_gpu>;

	qcom,gfxfreq-corner-v2 =

		<	   0  0  0 >,

		<  133000000  2  4 >,

arch/arm/boot/dts/qcom/msm8996.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -884,7 +884,7 @@ 
		reg = <0x8c0000 0xb00c>;

		reg-names = "cc_base";

		vdd_gfx-supply = <&gfx_vreg>;

		gpu_handle = <&msm_gpu>;

		qcom,gfx3d_clk_src-opp-handle = <&msm_gpu>;

		vdd_mx-supply = <&pm8994_s2_corner>;

		vdd_gpu_mx-supply = <&pm8994_s2_corner>;

		qcom,gfxfreq-corner-v0 =

drivers/clk/msm/clock-mmss-8996.c

+2 −77
Original line number Diff line number Diff line
@@ -19,7 +19,6 @@ 
#include <linux/clk/msm-clk-provider.h>

#include <linux/clk/msm-clock-generic.h>

#include <linux/of_platform.h>

#include <linux/pm_opp.h>



#include <soc/qcom/clock-alpha-pll.h>

#include <soc/qcom/clock-pll.h>
@@ -3500,7 +3499,7 @@ static void msm_mmsscc_8996_v3_fixup(void) 
	video_subcore1_clk_src.c.fmax[VDD_DIG_HIGH] = 533000000;

}



static int is_v2_gpu, is_v3_gpu, is_v3_0_gpu;

static int is_v3_gpu;

static int gpu_pre_set_rate(struct clk *clk, unsigned long new_rate)

{

	struct msm_rpm_kvp kvp;
@@ -3597,79 +3596,6 @@ static int of_get_fmax_vdd_class(struct platform_device *pdev, struct clk *c, 
	return 0;

}



static void print_opp_table(struct device *dev)

{

	struct clk *gpu_clk = &gfx3d_clk_src.c;

	struct dev_pm_opp *opp;

	int i;



	if (is_v2_gpu || is_v3_gpu || is_v3_0_gpu)

		gpu_clk = &gfx3d_clk_src_v2.c;



	pr_info("OPP table for GPU core clock:\n");

	for (i = 1; i < gpu_clk->num_fmax; i++) {

		if (!gpu_clk->fmax[i])

			continue;

		opp = dev_pm_opp_find_freq_exact(dev, gpu_clk->fmax[i], true);

		pr_info("clock-gpu: OPP voltage for %lu Hz: %ld uV\n",

			gpu_clk->fmax[i], dev_pm_opp_get_voltage(opp));

	}

}



static void populate_gpu_opp_table(struct platform_device *pdev)

{

	struct device_node *of = pdev->dev.of_node;

	struct platform_device *gpu_dev;

	struct device_node *gpu_node;

	struct clk *gpu_clk = &gfx3d_clk_src.c;

	struct clk_vdd_class *vdd = gpu_clk->vdd_class;

	int i, ret, uv, corner;

	unsigned long rate = 0;



	if (is_v2_gpu || is_v3_gpu || is_v3_0_gpu) {

		gpu_clk = &gfx3d_clk_src_v2.c;

		vdd = gpu_clk->vdd_class;

	}



	gpu_node = of_parse_phandle(of, "gpu_handle", 0);

	if (!gpu_node) {

		pr_err("clock-gpu: %s: Unable to get device_node pointer for GPU\n",

							__func__);

		return;

	}



	gpu_dev = of_find_device_by_node(gpu_node);

	if (!gpu_dev) {

		pr_err("clock-gpu: %s: Unable to find platform_device node for GPU\n",

							__func__);

		return;

	}



	for (i = 0; i < gpu_clk->num_fmax; i++) {

		if (!gpu_clk->fmax[i])

			continue;



		rate = gpu_clk->fmax[i];

		corner = vdd->vdd_uv[2 * i];

		uv = regulator_list_corner_voltage(vdd_gfx.regulator[0],

								corner);

		if (uv < 0) {

			pr_warn("clock-gpu: %s: no uv for corner %d - err: %d\n",

							__func__, corner, uv);

			return;

		}



		ret = dev_pm_opp_add(&gpu_dev->dev, rate, uv);

		if (ret) {

			pr_warn("clock-gpu: %s: couldn't add OPP for %lu - err: %d\n",

							__func__, rate, ret);

			return;

		}

	}



	print_opp_table(&gpu_dev->dev);

}



static struct platform_driver msm_clock_gpu_driver;



int msm_mmsscc_8996_probe(struct platform_device *pdev)
@@ -3867,6 +3793,7 @@ int msm_gpucc_8996_probe(struct platform_device *pdev) 
	struct resource *res;

	int rc;

	struct regulator *reg;

	int is_v2_gpu, is_v3_0_gpu;



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");

	if (!res) {
@@ -3959,8 +3886,6 @@ int msm_gpucc_8996_probe(struct platform_device *pdev) 
	}



	dev_info(&pdev->dev, "Registered GPU clocks.\n");



	populate_gpu_opp_table(pdev);

	return 0;

}