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Commit d45aa177 authored by Taniya Das's avatar Taniya Das
Browse files

clk: msm: clock-gcc: Fix sibling for mdp and jpeg0 clock 



The clocks of mdp and jpeg branch clock set rates would fail in case the
sibling is set. Also fix the blsp2_uart div values and the external parent
for byte clock.

Change-Id: I65ccc0dc9d941562b8f65a263d2e40e7fceb41c1
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 1c2c6d7f

drivers/clk/msm/clock-gcc-titanium.c

+10 −10
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -826,7 +826,7 @@ static struct clk_freq_tbl ftbl_blsp_uart_apps_clk_src[] = { 
	F(  56000000,           gpll0,    1,    7,   100),

	F(  58982400,           gpll0,    1, 1152, 15625),

	F(  60000000,           gpll0,    1,    3,    40),

	F(  64000000,           gpll0, 12.5,    1,     1),

	F(  64000000,           gpll0,    1,    2,    25),

	F_END

};
@@ -1387,13 +1387,13 @@ static struct clk_freq_tbl ftbl_byte0_clk_src[] = { 
	{

		.div_src_val = BVAL(10, 8, dsi0_phypll_mm_src_val)

					| BVAL(4, 0, 0),

		.src_clk = &ext_pclk0_clk_src.c,

		.src_clk = &ext_byte0_clk_src.c,

		.freq_hz = 0,

	},

	{

		.div_src_val = BVAL(10, 8, dsi1_phypll_mm_src_val)

					| BVAL(4, 0, 0),

		.src_clk = &ext_pclk1_clk_src.c,

		.src_clk = &ext_byte1_clk_src.c,

		.freq_hz = 0,

	},

	F_END
@@ -1425,13 +1425,13 @@ static struct clk_freq_tbl ftbl_byte1_clk_src[] = { 
	{

		.div_src_val = BVAL(10, 8, dsi1_phypll_clk_mm_src_val)

					| BVAL(4, 0, 0),

		.src_clk = &ext_pclk1_clk_src.c,

		.src_clk = &ext_byte1_clk_src.c,

		.freq_hz = 0,

	},

	{

		.div_src_val = BVAL(10, 8, dsi0_phypll_clk_mm_src_val)

					| BVAL(4, 0, 0),

		.src_clk = &ext_pclk0_clk_src.c,

		.src_clk = &ext_byte0_clk_src.c,

		.freq_hz = 0,

	},

	F_END
@@ -2278,7 +2278,7 @@ static struct branch_clk gcc_camss_ispif_ahb_clk = { 


static struct branch_clk gcc_camss_jpeg0_clk = {

	.cbcr_reg = CAMSS_JPEG0_CBCR,

	.has_sibling = 1,

	.has_sibling = 0,

	.base = &virt_bases[GCC_BASE],

	.c = {

		.dbg_name = "gcc_camss_jpeg0_clk",
@@ -2622,7 +2622,7 @@ static struct branch_clk gcc_mdss_esc1_clk = { 


static struct branch_clk gcc_mdss_mdp_clk = {

	.cbcr_reg = MDSS_MDP_CBCR,

	.has_sibling = 1,

	.has_sibling = 0,

	.base = &virt_bases[GCC_BASE],

	.c = {

		.dbg_name = "gcc_mdss_mdp_clk",
@@ -2637,7 +2637,7 @@ static DEFINE_CLK_VOTER(mdss_rotator_vote_clk, &gcc_mdss_mdp_clk.c, 0); 


static struct branch_clk gcc_mdss_pclk0_clk = {

	.cbcr_reg = MDSS_PCLK0_CBCR,

	.has_sibling = 1,

	.has_sibling = 0,

	.base = &virt_bases[MDSS_BASE],

	.c = {

		.dbg_name = "gcc_mdss_pclk0_clk",
@@ -2650,7 +2650,7 @@ static struct branch_clk gcc_mdss_pclk0_clk = { 


static struct branch_clk gcc_mdss_pclk1_clk = {

	.cbcr_reg = MDSS_PCLK1_CBCR,

	.has_sibling = 1,

	.has_sibling = 0,

	.base = &virt_bases[MDSS_BASE],

	.c = {

		.dbg_name = "gcc_mdss_pclk1_clk",