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Commit d4457361 authored by Phani Kumar Uppalapati's avatar Phani Kumar Uppalapati Committed by Sudheer Papothi
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ASoC: msm: qdsp6v2: Add support to send codec page config



Q6 DSP will have to access WCD codec registers for few
audio features like speaker protection, active noise
cancellation etc. To access the WCD codec registers,
Q6 DSP will have to know whether WCD codec has register
paging or not. Add an API in afe driver to send the codec
register page related information to the Q6 DSP so that
it can access the codec registers.

Change-Id: I8d5b6fc65986744ec3e484d59fdf5ce24d463c07
Signed-off-by: default avatarPhani Kumar Uppalapati <phaniu@codeaurora.org>
Signed-off-by: default avatarSudheer Papothi <spapothi@codeaurora.org>
parent fd854d74
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+24 −0
Original line number Diff line number Diff line
@@ -7284,6 +7284,7 @@ struct asm_dts_eagle_param_get {
#define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG		(0x00010235)
#define AFE_PARAM_ID_CDC_REG_CFG			(0x00010236)
#define AFE_PARAM_ID_CDC_REG_CFG_INIT			(0x00010237)
#define AFE_PARAM_ID_CDC_REG_PAGE_CFG                   (0x00010296)

#define AFE_MAX_CDC_REGISTERS_TO_CONFIG			(20)

@@ -7706,6 +7707,7 @@ enum afe_config_type {
	AFE_AANC_VERSION,
	AFE_CDC_CLIP_REGISTERS_CONFIG,
	AFE_CLIP_BANK_SEL,
	AFE_CDC_REGISTER_PAGE_CONFIG,
	AFE_MAX_CONFIG_TYPES,
};

@@ -7737,6 +7739,21 @@ struct afe_param_cdc_reg_cfg {
	uint16_t reg_offset_scale;
} __packed;

#define AFE_API_VERSION_CDC_REG_PAGE_CFG   1

enum {
	AFE_CDC_REG_PAGE_ASSIGN_PROC_ID_0 = 0,
	AFE_CDC_REG_PAGE_ASSIGN_PROC_ID_1,
	AFE_CDC_REG_PAGE_ASSIGN_PROC_ID_2,
	AFE_CDC_REG_PAGE_ASSIGN_PROC_ID_3,
};

struct afe_param_cdc_reg_page_cfg {
	uint32_t minor_version;
	uint32_t enable;
	uint32_t proc_id;
} __packed;

struct afe_param_cdc_reg_cfg_data {
	uint32_t num_registers;
	struct afe_param_cdc_reg_cfg *reg_data;
@@ -7816,6 +7833,13 @@ struct afe_svc_cmd_sb_slave_cfg {
	struct afe_param_cdc_slimbus_slave_cfg sb_slave_cfg;
} __packed;

struct afe_svc_cmd_cdc_reg_page_cfg {
	struct apr_hdr hdr;
	struct afe_svc_cmd_set_param param;
	struct afe_port_param_data_v2 pdata;
	struct afe_param_cdc_reg_page_cfg cdc_reg_page_cfg;
} __packed;

struct afe_svc_cmd_cdc_aanc_version {
	struct apr_hdr hdr;
	struct afe_svc_cmd_set_param param;
+36 −0
Original line number Diff line number Diff line
@@ -1214,6 +1214,39 @@ static int afe_send_slimbus_slave_cfg(
	return ret;
}

static int afe_send_codec_reg_page_config(
	struct afe_param_cdc_reg_page_cfg *cdc_reg_page_cfg)
{
	struct afe_svc_cmd_cdc_reg_page_cfg config;
	int ret;

	config.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
					     APR_HDR_LEN(APR_HDR_SIZE),
					     APR_PKT_VER);
	config.hdr.pkt_size = sizeof(config);
	config.hdr.src_port = 0;
	config.hdr.dest_port = 0;
	config.hdr.token = IDX_GLOBAL_CFG;
	config.hdr.opcode = AFE_SVC_CMD_SET_PARAM;
	config.param.payload_size = sizeof(config) - sizeof(struct apr_hdr) -
				    sizeof(config.param);
	config.param.payload_address_lsw = 0x00;
	config.param.payload_address_msw = 0x00;
	config.param.mem_map_handle = 0x00;
	config.pdata.module_id = AFE_MODULE_CDC_DEV_CFG;
	config.pdata.param_id = AFE_PARAM_ID_CDC_REG_PAGE_CFG;
	config.pdata.param_size =
	    sizeof(struct afe_param_cdc_reg_page_cfg);
	config.cdc_reg_page_cfg = *cdc_reg_page_cfg;

	ret = afe_apr_send_pkt(&config, &this_afe.wait[IDX_GLOBAL_CFG]);
	if (ret)
		pr_err("%s: AFE_PARAM_ID_CDC_REG_PAGE_CFG failed %d\n",
		       __func__, ret);

	return ret;
}

static int afe_send_codec_reg_config(
	struct afe_param_cdc_reg_cfg_data *cdc_reg_cfg)
{
@@ -1617,6 +1650,9 @@ int afe_set_config(enum afe_config_type config_type, void *config_data, int arg)
	case AFE_CDC_CLIP_REGISTERS_CONFIG:
		ret = afe_send_codec_reg_config(config_data);
		break;
	case AFE_CDC_REGISTER_PAGE_CONFIG:
		ret = afe_send_codec_reg_page_config(config_data);
		break;
	default:
		pr_err("%s: unknown configuration type %d",
			__func__, config_type);