Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d37b5850 authored by Sahitya Tummala's avatar Sahitya Tummala
Browse files

mmc: core: fix issue with devfreq clock scaling 



Due to recent DDR52 lower bus speed mode in clock scaling,
there is a mismatch between the clock frequencies used by
the devfreq framework and the MMC driver. Due to this, SDCC
clock is sometimes running at DDR25 and ICE clock is running
at 100MHz causing the power regression. Fix this mismatch by
initializing the frequencies properly during MMC resume based
on the current ios.clock.

CRs-Fixed: 974940
Change-Id: I09fe888d0fbd1fde3f6a6f32806315ddbb5bf6e1
Signed-off-by: default avatarSahitya Tummala <stummala@codeaurora.org>
parent 1c10389d

drivers/mmc/core/core.c

+12 −1
Original line number Diff line number Diff line
@@ -773,6 +773,9 @@ EXPORT_SYMBOL(mmc_suspend_clk_scaling); 
int mmc_resume_clk_scaling(struct mmc_host *host)

{

	int err = 0;

	u32 max_clk_idx = 0;

	u32 devfreq_max_clk = 0;

	u32 devfreq_min_clk = 0;



	if (!host) {

		WARN(1, "bad host parameter\n");
@@ -789,7 +792,15 @@ int mmc_resume_clk_scaling(struct mmc_host *host) 
	}



	atomic_set(&host->clk_scaling.devfreq_abort, 0);

	host->clk_scaling.curr_freq = host->ios.clock;



	max_clk_idx = host->clk_scaling.freq_table_sz - 1;

	devfreq_max_clk = host->clk_scaling.freq_table[max_clk_idx];

	devfreq_min_clk = host->clk_scaling.freq_table[0];



	host->clk_scaling.curr_freq = devfreq_max_clk;

	if (host->ios.clock < host->card->clk_scaling_highest)

		host->clk_scaling.curr_freq = devfreq_min_clk;



	host->clk_scaling.clk_scaling_in_progress = false;

	host->clk_scaling.need_freq_change = false;