Commit d36bec4c authored May 12, 2015 by Joe Konno Committed by Sasha Levin Jul 03, 2015

intel_pstate: set BYT MSR with wrmsrl_on_cpu()



[ Upstream commit 0dd23f94251f49da99a6cbfb22418b2d757d77d6 ]

Commit 007bea09 (intel_pstate: Add setting voltage value for
baytrail P states.) introduced byt_set_pstate() with the assumption that
it would always be run by the CPU whose MSR is to be written by it.  It
turns out, however, that is not always the case in practice, so modify
byt_set_pstate() to enforce the MSR write done by it to always happen on
the right CPU.

Fixes: 007bea09 (intel_pstate: Add setting voltage value for baytrail P states.)
Signed-off-by: Joe Konno <joe.konno@intel.com>
Acked-by: Kristen Carlson Accardi <kristen@linux.intel.com>
Cc: 3.14+ <stable@vger.kernel.org> # 3.14+
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>

parent f5ef1e8c

drivers/cpufreq/intel_pstate.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -443,7 +443,7 @@ static void byt_set_pstate(struct cpudata *cpudata, int pstate)

		val \|= vid;

		wrmsrl(MSR_IA32_PERF_CTL, val);
		wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val);
		}

		#define BYT_BCLK_FREQS 5