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Commit d30645ae authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-nouveau-next' of... 

Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next

Nothing major ready for merging yet, so mostly bug fixes below, in addition to VP3 enablement from Ilia.

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6:
  drm/nouveau: fix command submission to use vmalloc for big allocations
  drm/nouveau/bios/therm: handle vbioses with duplicate entries (mostly nva5)
  drm/nouveau: use MSI interrupts
  drm/nv50-/kms: assume analog display connected if load on any pin
  drm/nv50/disp: prevent false output detection on the original nv50
  drm/nouveau/i2c: pass the function pointers in at creation time
  drm/nouveau/therm: survive to suspend/resume cycles
  drm/nouveau/timer: add a way to cancel alarms
  drm/nouveau/timer: restore the time on resume
  drm/nouveau/fan: restore pwm value on resume when in manual/auto mode
  drm/nouveau/therm: Set the correct pwm_mode upon resume
  drm/nouveau: require contiguous bo for framebuffer
  drm/nv50-/disp: use the number of dac, sor, pior rather than hardcoded values
  drm/nouveau: remove duplicate copy of nv44_graph_class
  drm/nouveau/vdec: implement support for VP3 engines
  drm/nouveau/core: get rid of math.h, replace log2i with order_base_2
parents ef25bd84 c859074e

drivers/gpu/drm/nouveau/core/core/ramht.c

+1 −2
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ 


#include <core/object.h>

#include <core/ramht.h>

#include <core/math.h>



#include <subdev/bar.h>
@@ -104,6 +103,6 @@ nouveau_ramht_new(struct nouveau_object *parent, struct nouveau_object *pargpu, 
	if (ret)

		return ret;



	ramht->bits = log2i(nv_gpuobj(ramht)->size >> 3);

	ramht->bits = order_base_2(nv_gpuobj(ramht)->size >> 3);

	return 0;

}

drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c

+35 −17
Original line number Diff line number Diff line
@@ -19,16 +19,14 @@ 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs

 * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin

 */



#include <core/engctx.h>

#include <core/class.h>



#include <engine/falcon.h>

#include <engine/bsp.h>



struct nv98_bsp_priv {

	struct nouveau_engine base;

	struct nouveau_falcon base;

};



/*******************************************************************************
@@ -37,30 +35,48 @@ struct nv98_bsp_priv { 


static struct nouveau_oclass

nv98_bsp_sclass[] = {

	{ 0x88b1, &nouveau_object_ofuncs },

	{ 0x85b1, &nouveau_object_ofuncs },

	{ 0x86b1, &nouveau_object_ofuncs },

	{},

};



/*******************************************************************************

 * BSP context

 * PBSP context

 ******************************************************************************/



static struct nouveau_oclass

nv98_bsp_cclass = {

	.handle = NV_ENGCTX(BSP, 0x98),

	.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = _nouveau_engctx_ctor,

		.dtor = _nouveau_engctx_dtor,

		.init = _nouveau_engctx_init,

		.fini = _nouveau_engctx_fini,

		.rd32 = _nouveau_engctx_rd32,

		.wr32 = _nouveau_engctx_wr32,

		.ctor = _nouveau_falcon_context_ctor,

		.dtor = _nouveau_falcon_context_dtor,

		.init = _nouveau_falcon_context_init,

		.fini = _nouveau_falcon_context_fini,

		.rd32 = _nouveau_falcon_context_rd32,

		.wr32 = _nouveau_falcon_context_wr32,

	},

};



/*******************************************************************************

 * BSP engine/subdev functions

 * PBSP engine/subdev functions

 ******************************************************************************/



static int

nv98_bsp_init(struct nouveau_object *object)

{

	struct nv98_bsp_priv *priv = (void *)object;

	int ret;



	ret = nouveau_falcon_init(&priv->base);

	if (ret)

		return ret;



	nv_wr32(priv, 0x084010, 0x0000ffd2);

	nv_wr32(priv, 0x08401c, 0x0000fff2);

	return 0;

}



static int

nv98_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,

	      struct nouveau_oclass *oclass, void *data, u32 size,
@@ -69,7 +85,7 @@ nv98_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 
	struct nv98_bsp_priv *priv;

	int ret;



	ret = nouveau_engine_create(parent, engine, oclass, true,

	ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,

				    "PBSP", "bsp", &priv);

	*pobject = nv_object(priv);

	if (ret)
@@ -86,8 +102,10 @@ nv98_bsp_oclass = { 
	.handle = NV_ENGINE(BSP, 0x98),

	.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = nv98_bsp_ctor,

		.dtor = _nouveau_engine_dtor,

		.init = _nouveau_engine_init,

		.fini = _nouveau_engine_fini,

		.dtor = _nouveau_falcon_dtor,

		.init = nv98_bsp_init,

		.fini = _nouveau_falcon_fini,

		.rd32 = _nouveau_falcon_rd32,

		.wr32 = _nouveau_falcon_wr32,

	},

};

drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c

+10 −5
Original line number Diff line number Diff line
@@ -49,18 +49,23 @@ int 
nv50_dac_sense(struct nv50_disp_priv *priv, int or, u32 loadval)

{

	const u32 doff = (or * 0x800);

	int load = -EINVAL;



	nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000);

	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);



	nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval);

	mdelay(9);

	udelay(500);

	nv_wr32(priv, 0x61a00c + doff, 0x80000000);

	load = (nv_rd32(priv, 0x61a00c + doff) & 0x38000000) >> 27;

	nv_wr32(priv, 0x61a00c + doff, 0x00000000);

	loadval = nv_mask(priv, 0x61a00c + doff, 0xffffffff, 0x00000000);



	nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000);

	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);

	return load;



	nv_debug(priv, "DAC%d sense: 0x%08x\n", or, loadval);

	if (!(loadval & 0x80000000))

		return -ETIMEDOUT;



	return (loadval & 0x38000000) >> 27;

}



int

drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

+17 −17
Original line number Diff line number Diff line
@@ -628,7 +628,7 @@ nv50_disp_base_init(struct nouveau_object *object) 
	}



	/* ... PIOR caps */

	for (i = 0; i < 3; i++) {

	for (i = 0; i < priv->pior.nr; i++) {

		tmp = nv_rd32(priv, 0x61e000 + (i * 0x800));

		nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp);

	}
@@ -834,10 +834,11 @@ exec_script(struct nv50_disp_priv *priv, int head, int id) 
	u8  ver, hdr, cnt, len;

	u16 data;

	u32 ctrl = 0x00000000;

	u32 reg;

	int i;



	/* DAC */

	for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)

	for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++)

		ctrl = nv_rd32(priv, 0x610b5c + (i * 8));



	/* SOR */
@@ -845,19 +846,18 @@ exec_script(struct nv50_disp_priv *priv, int head, int id) 
		if (nv_device(priv)->chipset  < 0x90 ||

		    nv_device(priv)->chipset == 0x92 ||

		    nv_device(priv)->chipset == 0xa0) {

			for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)

				ctrl = nv_rd32(priv, 0x610b74 + (i * 8));

			i += 4;

			reg = 0x610b74;

		} else {

			for (i = 0; !(ctrl & (1 << head)) && i < 4; i++)

				ctrl = nv_rd32(priv, 0x610798 + (i * 8));

			i += 4;

			reg = 0x610798;

		}

		for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++)

			ctrl = nv_rd32(priv, reg + (i * 8));

		i += 4;

	}



	/* PIOR */

	if (!(ctrl & (1 << head))) {

		for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)

		for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++)

			ctrl = nv_rd32(priv, 0x610b84 + (i * 8));

		i += 8;

	}
@@ -893,10 +893,11 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, 
	u8  ver, hdr, cnt, len;

	u32 ctrl = 0x00000000;

	u32 data, conf = ~0;

	u32 reg;

	int i;



	/* DAC */

	for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)

	for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++)

		ctrl = nv_rd32(priv, 0x610b58 + (i * 8));



	/* SOR */
@@ -904,19 +905,18 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, 
		if (nv_device(priv)->chipset  < 0x90 ||

		    nv_device(priv)->chipset == 0x92 ||

		    nv_device(priv)->chipset == 0xa0) {

			for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)

				ctrl = nv_rd32(priv, 0x610b70 + (i * 8));

			i += 4;

			reg = 0x610b70;

		} else {

			for (i = 0; !(ctrl & (1 << head)) && i < 4; i++)

				ctrl = nv_rd32(priv, 0x610794 + (i * 8));

			i += 4;

			reg = 0x610794;

		}

		for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++)

			ctrl = nv_rd32(priv, reg + (i * 8));

		i += 4;

	}



	/* PIOR */

	if (!(ctrl & (1 << head))) {

		for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)

		for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++)

			ctrl = nv_rd32(priv, 0x610b80 + (i * 8));

		i += 8;

	}

drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c

+1 −2
Original line number Diff line number Diff line
@@ -26,7 +26,6 @@ 
#include <core/engctx.h>

#include <core/ramht.h>

#include <core/class.h>

#include <core/math.h>



#include <subdev/timer.h>

#include <subdev/bar.h>
@@ -278,7 +277,7 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent, 
		return ret;



	ioffset = args->ioffset;

	ilength = log2i(args->ilength / 8);

	ilength = order_base_2(args->ilength / 8);



	nv_wo32(base->ramfc, 0x3c, 0x403f6078);

	nv_wo32(base->ramfc, 0x44, 0x01003fff);