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Commit d2f78e95 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Vinod Koul
Browse files

dmaengine: dw: enable clock before access 



hclk signal is a bus clock. So, it means we have to have it enabled during
access to the DMA controller. This patch makes sure that we enable clock before
access to the device, though it currently works on Intel hardware.

Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent fbeb91fe

drivers/dma/dw/core.c

+5 −5
Original line number Diff line number Diff line
@@ -1493,6 +1493,11 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) 
	dw->regs = chip->regs;

	chip->dw = dw;



	dw->clk = devm_clk_get(chip->dev, "hclk");

	if (IS_ERR(dw->clk))

		return PTR_ERR(dw->clk);

	clk_prepare_enable(dw->clk);



	dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);

	autocfg = dw_params >> DW_PARAMS_EN & 0x1;
@@ -1520,11 +1525,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) 
	if (!dw->chan)

		return -ENOMEM;



	dw->clk = devm_clk_get(chip->dev, "hclk");

	if (IS_ERR(dw->clk))

		return PTR_ERR(dw->clk);

	clk_prepare_enable(dw->clk);



	/* Get hardware configuration parameters */

	if (autocfg) {

		max_blk_size = dma_readl(dw, MAX_BLK_SIZE);