Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d2c7ef95 authored by Sagar Gore's avatar Sagar Gore
Browse files

msm: camera: isp: Dual vfe enable write master sync 



In case of non bundled stream on, sensor is already streaming
hence enabling of write master in kernel is done at sof irq.
Userspace session thread waits till sof before issuing start
axi to kernel but due to timing delays this is received very
close to next sof. This causes one vfe to enable write master
before the other. In short  write masters of two vfes get enabled
across frame boundary which reults in split.
This fix enables write masters from single thread of right vfe
to maintain both vfes in sync.

Change-Id: If3b278de80d075cced6435fff5e073323a57643b
Signed-off-by: default avatarSagar Gore <sgore@codeaurora.org>
parent 0dab3364

drivers/media/platform/msm/camera_v2/isp/msm_isp.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -145,7 +145,7 @@ struct msm_vfe_irq_ops { 
struct msm_vfe_axi_ops {

struct msm_vfe_axi_ops {

	void (*reload_wm)(struct vfe_device *vfe_dev, void __iomem *vfe_base,

	void (*reload_wm)(struct vfe_device *vfe_dev, void __iomem *vfe_base,

		uint32_t reload_mask);

		uint32_t reload_mask);

	void (*enable_wm)(struct vfe_device *vfe_dev,

	void (*enable_wm)(void __iomem *vfe_base,

		uint8_t wm_idx, uint8_t enable);

		uint8_t wm_idx, uint8_t enable);

	int32_t (*cfg_io_format)(struct vfe_device *vfe_dev,

	int32_t (*cfg_io_format)(struct vfe_device *vfe_dev,

		enum msm_vfe_axi_stream_src stream_src,

		enum msm_vfe_axi_stream_src stream_src,

drivers/media/platform/msm/camera_v2/isp/msm_isp32.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -682,17 +682,17 @@ static void msm_vfe32_axi_reload_wm( 
	}

	}

}

}





static void msm_vfe32_axi_enable_wm(struct vfe_device *vfe_dev,

static void msm_vfe32_axi_enable_wm(void __iomem *vfe_base,

	uint8_t wm_idx, uint8_t enable)

	uint8_t wm_idx, uint8_t enable)

{

{

	uint32_t val = msm_camera_io_r(

	uint32_t val = msm_camera_io_r(

	   vfe_dev->vfe_base + VFE32_WM_BASE(wm_idx));

	   vfe_base + VFE32_WM_BASE(wm_idx));

	if (enable)

	if (enable)

		val |= 0x1;

		val |= 0x1;

	else

	else

		val &= ~0x1;

		val &= ~0x1;

	msm_camera_io_w_mb(val,

	msm_camera_io_w_mb(val,

		vfe_dev->vfe_base + VFE32_WM_BASE(wm_idx));

		vfe_base + VFE32_WM_BASE(wm_idx));

}

}





static void msm_vfe32_axi_cfg_comp_mask(struct vfe_device *vfe_dev,

static void msm_vfe32_axi_cfg_comp_mask(struct vfe_device *vfe_dev,

drivers/media/platform/msm/camera_v2/isp/msm_isp40.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -835,17 +835,17 @@ static void msm_vfe40_axi_update_cgc_override(struct vfe_device *vfe_dev, 
	msm_camera_io_w_mb(val, vfe_dev->vfe_base + 0x974);

	msm_camera_io_w_mb(val, vfe_dev->vfe_base + 0x974);

}

}





static void msm_vfe40_axi_enable_wm(struct vfe_device *vfe_dev,

static void msm_vfe40_axi_enable_wm(void __iomem *vfe_base,

	uint8_t wm_idx, uint8_t enable)

	uint8_t wm_idx, uint8_t enable)

{

{

	uint32_t val;

	uint32_t val;

	val = msm_camera_io_r(vfe_dev->vfe_base + VFE40_WM_BASE(wm_idx));

	val = msm_camera_io_r(vfe_base + VFE40_WM_BASE(wm_idx));

	if (enable)

	if (enable)

		val |= 0x1;

		val |= 0x1;

	else

	else

		val &= ~0x1;

		val &= ~0x1;

	msm_camera_io_w_mb(val,

	msm_camera_io_w_mb(val,

		vfe_dev->vfe_base + VFE40_WM_BASE(wm_idx));

		vfe_base + VFE40_WM_BASE(wm_idx));

}

}





static void msm_vfe40_axi_cfg_comp_mask(struct vfe_device *vfe_dev,

static void msm_vfe40_axi_cfg_comp_mask(struct vfe_device *vfe_dev,

drivers/media/platform/msm/camera_v2/isp/msm_isp44.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -672,17 +672,17 @@ static void msm_vfe44_axi_reload_wm(struct vfe_device *vfe_dev, 
	msm_camera_io_w_mb(reload_mask, vfe_base + 0x4C);

	msm_camera_io_w_mb(reload_mask, vfe_base + 0x4C);

}

}





static void msm_vfe44_axi_enable_wm(struct vfe_device *vfe_dev,

static void msm_vfe44_axi_enable_wm(void __iomem *vfe_base,

	uint8_t wm_idx, uint8_t enable)

	uint8_t wm_idx, uint8_t enable)

{

{

	uint32_t val;

	uint32_t val;

	val = msm_camera_io_r(vfe_dev->vfe_base + VFE44_WM_BASE(wm_idx));

	val = msm_camera_io_r(vfe_base + VFE44_WM_BASE(wm_idx));

	if (enable)

	if (enable)

		val |= 0x1;

		val |= 0x1;

	else

	else

		val &= ~0x1;

		val &= ~0x1;

	msm_camera_io_w_mb(val,

	msm_camera_io_w_mb(val,

		vfe_dev->vfe_base + VFE44_WM_BASE(wm_idx));

		vfe_base + VFE44_WM_BASE(wm_idx));

}

}





static void msm_vfe44_axi_update_cgc_override(struct vfe_device *vfe_dev,

static void msm_vfe44_axi_update_cgc_override(struct vfe_device *vfe_dev,

drivers/media/platform/msm/camera_v2/isp/msm_isp46.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -615,18 +615,18 @@ static void msm_vfe46_axi_update_cgc_override(struct vfe_device *vfe_dev, 
	msm_camera_io_w_mb(val, vfe_dev->vfe_base + 0x3C);

	msm_camera_io_w_mb(val, vfe_dev->vfe_base + 0x3C);

}

}





static void msm_vfe46_axi_enable_wm(struct vfe_device *vfe_dev,

static void msm_vfe46_axi_enable_wm(void __iomem *vfe_base,

	uint8_t wm_idx, uint8_t enable)

	uint8_t wm_idx, uint8_t enable)

{

{

	uint32_t val;

	uint32_t val;





	val = msm_camera_io_r(vfe_dev->vfe_base + VFE46_WM_BASE(wm_idx));

	val = msm_camera_io_r(vfe_base + VFE46_WM_BASE(wm_idx));

	if (enable)

	if (enable)

		val |= 0x1;

		val |= 0x1;

	else

	else

		val &= ~0x1;

		val &= ~0x1;

	msm_camera_io_w_mb(val,

	msm_camera_io_w_mb(val,

		vfe_dev->vfe_base + VFE46_WM_BASE(wm_idx));

		vfe_base + VFE46_WM_BASE(wm_idx));

}

}





static void msm_vfe46_axi_cfg_comp_mask(struct vfe_device *vfe_dev,

static void msm_vfe46_axi_cfg_comp_mask(struct vfe_device *vfe_dev,