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Commit d2c4e6ab authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: add hardware event support for mdmfermium"

parents d9216fbe 14d97c56

arch/arm/boot/dts/qcom/mdmfermium-coresight.dtsi

+215 −2
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
		coresight-id = <0>;

		coresight-name = "coresight-tmc-etr";

		coresight-nr-inports = <1>;

		coresight-ctis = <&cti0 &cti8>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -59,6 +60,7 @@ 
		coresight-child-list = <&replicator>;

		coresight-child-ports = <0>;

		coresight-default-sink;

		coresight-ctis = <&cti0 &cti8>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -99,13 +101,184 @@ 
		clock-names = "core_clk", "core_a_clk";

	};



	cti0: cti@6010000 {

		compatible = "arm,coresight-cti";

		reg = <0x6010000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <5>;

		coresight-name = "coresight-cti0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti1: cti@6011000 {

		compatible = "arm,coresight-cti";

		reg = <0x6011000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <6>;

		coresight-name = "coresight-cti1";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti2: cti@6012000 {

		compatible = "arm,coresight-cti";

		reg = <0x6012000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <7>;

		coresight-name = "coresight-cti2";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti3: cti@6013000 {

		compatible = "arm,coresight-cti";

		reg = <0x6013000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <8>;

		coresight-name = "coresight-cti3";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti4: cti@6014000 {

		compatible = "arm,coresight-cti";

		reg = <0x6014000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <9>;

		coresight-name = "coresight-cti4";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti5: cti@6015000 {

		compatible = "arm,coresight-cti";

		reg = <0x6015000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <10>;

		coresight-name = "coresight-cti5";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti6: cti@6016000 {

		compatible = "arm,coresight-cti";

		reg = <0x6016000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <11>;

		coresight-name = "coresight-cti6";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti7: cti@6017000 {

		compatible = "arm,coresight-cti";

		reg = <0x6017000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <12>;

		coresight-name = "coresight-cti7";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti8: cti@6018000 {

		compatible = "arm,coresight-cti";

		reg = <0x6018000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <13>;

		coresight-name = "coresight-cti8";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu0: cti@6043000 {

		compatible = "arm,coresight-cti";

		reg = <0x6043000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <14>;

		coresight-name = "coresight-cti-cpu0";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU0>;



		qcom,cti-save;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_rpm_cpu0: cti@603c000 {

		compatible = "arm,coresight-cti";

		reg = <0x603c000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <15>;

		coresight-name = "coresight-cti-rpm-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_modem_cpu0: cti@6038000 {

		compatible = "arm,coresight-cti";

		reg = <0x6038000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <16>;

		coresight-name = "coresight-cti-modem-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	stm: stm@6002000 {

		compatible = "arm,coresight-stm";

		reg = <0x6002000 0x1000>,

		      <0x9280000 0x180000>;

		reg-names = "stm-base", "stm-data-base";



		coresight-id = <5>;

		coresight-id = <17>;

		coresight-name = "coresight-stm";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;
@@ -122,7 +295,7 @@ 
		reg = <0x6001000 0x1000>;

		reg-names = "csr-base";



		coresight-id = <6>;

		coresight-id = <18>;

		coresight-name = "coresight-csr";

		coresight-nr-inports = <0>;
@@ -132,4 +305,44 @@ 
			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm0: etm@6042000 {

		compatible = "arm,coresight-etm";

		reg = <0x6042000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <19>;

		coresight-name = "coresight-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <4>;

		coresight-etm-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	hwevent: hwevent@606c000 {

		compatible = "qcom,coresight-hwevent";

		reg = <0x606c000 0x148>,

		      <0x606cfb0 0x4>,

		      <0x78640cc 0x4>,

		      <0x78240cc 0x4>,

		      <0x7885010 0x4>,

		      <0x200c004 0x4>,

		      <0x78d90a0 0x4>;

		reg-names = "wrapper-mux", "wrapper-lockaccess",

			    "wrapper-sdcc2", "wrapper-sdcc1",

			    "blsp-mux", "spmi-mux" ,"usb-mux";



		coresight-id = <20>;

		coresight-name = "coresight-hwevent";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};

};