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Commit d28e6d2e authored by Arun KS's avatar Arun KS
Browse files

soc: qcom: pil: Proxy vote for QPIC clock during modem boot 



On MDM targets, QPIC clock need to be enabled during modem boot.
On cold boot, RPM sets the proxy vote for modem. But during a SSR,
HLOS needs to proxy vote. Put in a proxy vote from HLOS PIL which
is removed once the modem boots up.

Change-Id: I02d5ad5c68e922683d53f38070df672200c0d933
Signed-off-by: default avatarArun KS <arunks@codeaurora.org>
parent cc957303

drivers/soc/qcom/pil-q6v5.c

+13 −0
Original line number Diff line number Diff line
@@ -101,6 +101,12 @@ int pil_q6v5_make_proxy_votes(struct pil_desc *pil) 
		goto out;

	}



	ret = clk_prepare_enable(drv->qpic_clk);

	if (ret) {

		dev_err(pil->dev, "Failed to vote for qpic clk\n");

		goto err_qpic_vote;

	}



	ret = clk_prepare_enable(drv->pnoc_clk);

	if (ret) {

		dev_err(pil->dev, "Failed to vote for pnoc\n");
@@ -152,6 +158,8 @@ err_cx_voltage: 
err_qdss_vote:

	clk_disable_unprepare(drv->pnoc_clk);

err_pnoc_vote:

	clk_disable_unprepare(drv->qpic_clk);

err_qpic_vote:

	clk_disable_unprepare(drv->xo);

out:

	return ret;
@@ -177,6 +185,7 @@ void pil_q6v5_remove_proxy_votes(struct pil_desc *pil) 
	regulator_set_optimum_mode(drv->vreg_cx, 0);

	regulator_set_voltage(drv->vreg_cx, RPM_REGULATOR_CORNER_NONE, INT_MAX);

	clk_disable_unprepare(drv->xo);

	clk_disable_unprepare(drv->qpic_clk);

	clk_disable_unprepare(drv->pnoc_clk);

	clk_disable_unprepare(drv->qdss_clk);

}
@@ -674,6 +683,10 @@ struct q6v5_data *pil_q6v5_init(struct platform_device *pdev) 
	if (IS_ERR(drv->xo))

		return ERR_CAST(drv->xo);



	drv->qpic_clk = devm_clk_get(&pdev->dev, "qpic");

	if (IS_ERR(drv->qpic_clk))

		drv->qpic_clk = NULL;



	if (of_property_read_bool(pdev->dev.of_node, "qcom,pnoc-clk-vote")) {

		drv->pnoc_clk = devm_clk_get(&pdev->dev, "pnoc_clk");

		if (IS_ERR(drv->pnoc_clk))

drivers/soc/qcom/pil-q6v5.h

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ struct q6v5_data { 
	struct clk *snoc_axi_clk;

	struct clk *mnoc_axi_clk;

	struct clk *qdss_clk;

	struct clk *qpic_clk;

	void __iomem *axi_halt_base; /* Halt base of q6, mss,

					nc are in same 4K page */

	void __iomem *axi_halt_q6;