Loading Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt +6 −8 Original line number Diff line number Diff line Loading @@ -4,17 +4,15 @@ Available on Marvell SOCs: Armada 370 and Armada XP Required properties: - compatible: "marvell,armada-370-xp-pmsu" - compatible: should be "marvell,armada-370-pmsu", whereas "marvell,armada-370-xp-pmsu" is deprecated and will be removed - reg: Should contain PMSU registers location and length. First pair for the per-CPU SW Reset Control registers, second pair for the Power Management Service Unit. - reg: Should contain PMSU registers location and length. Example: armada-370-xp-pmsu@d0022000 { compatible = "marvell,armada-370-xp-pmsu"; reg = <0xd0022100 0x430>, <0xd0020800 0x20>; armada-370-xp-pmsu@22000 { compatible = "marvell,armada-370-pmsu"; reg = <0x22000 0x1000>; }; Documentation/devicetree/bindings/arm/armada-cpu-reset.txt 0 → 100644 +14 −0 Original line number Diff line number Diff line Marvell Armada CPU reset controller =================================== Required properties: - compatible: Should be "marvell,armada-370-cpu-reset". - reg: should be register base and length as documented in the datasheet for the CPU reset registers cpurst: cpurst@20800 { compatible = "marvell,armada-370-cpu-reset"; reg = <0x20800 0x20>; }; arch/arm/mach-mvebu/Makefile +1 −1 Original line number Diff line number Diff line Loading @@ -3,7 +3,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ AFLAGS_coherency_ll.o := -Wa,-march=armv7-a obj-y += system-controller.o mvebu-soc-id.o obj-y += system-controller.o mvebu-soc-id.o cpu-reset.o obj-$(CONFIG_MACH_MVEBU_V7) += board-v7.o obj-$(CONFIG_MACH_DOVE) += dove.o obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o Loading arch/arm/mach-mvebu/common.h +1 −0 Original line number Diff line number Diff line Loading @@ -18,6 +18,7 @@ #include <linux/reboot.h> void mvebu_restart(enum reboot_mode mode, const char *cmd); int mvebu_cpu_reset_deassert(int cpu); void armada_xp_cpu_die(unsigned int cpu); Loading arch/arm/mach-mvebu/cpu-reset.c 0 → 100644 +103 −0 Original line number Diff line number Diff line /* * Copyright (C) 2014 Marvell * * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ #define pr_fmt(fmt) "mvebu-cpureset: " fmt #include <linux/kernel.h> #include <linux/init.h> #include <linux/of_address.h> #include <linux/io.h> #include <linux/resource.h> #include "armada-370-xp.h" static void __iomem *cpu_reset_base; static size_t cpu_reset_size; #define CPU_RESET_OFFSET(cpu) (cpu * 0x8) #define CPU_RESET_ASSERT BIT(0) int mvebu_cpu_reset_deassert(int cpu) { u32 reg; if (!cpu_reset_base) return -ENODEV; if (CPU_RESET_OFFSET(cpu) >= cpu_reset_size) return -EINVAL; reg = readl(cpu_reset_base + CPU_RESET_OFFSET(cpu)); reg &= ~CPU_RESET_ASSERT; writel(reg, cpu_reset_base + CPU_RESET_OFFSET(cpu)); return 0; } static int mvebu_cpu_reset_map(struct device_node *np, int res_idx) { struct resource res; if (of_address_to_resource(np, res_idx, &res)) { pr_err("unable to get resource\n"); return -ENOENT; } if (!request_mem_region(res.start, resource_size(&res), np->full_name)) { pr_err("unable to request region\n"); return -EBUSY; } cpu_reset_base = ioremap(res.start, resource_size(&res)); if (!cpu_reset_base) { pr_err("unable to map registers\n"); release_mem_region(res.start, resource_size(&res)); return -ENOMEM; } cpu_reset_size = resource_size(&res); return 0; } int __init mvebu_cpu_reset_init(void) { struct device_node *np; int res_idx; int ret; np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-cpu-reset"); if (np) { res_idx = 0; } else { /* * This code is kept for backward compatibility with * old Device Trees. */ np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-pmsu"); if (np) { pr_warn(FW_WARN "deprecated pmsu binding\n"); res_idx = 1; } } /* No reset node found */ if (!np) return -ENODEV; ret = mvebu_cpu_reset_map(np, res_idx); of_node_put(np); return ret; } early_initcall(mvebu_cpu_reset_init); Loading
Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt +6 −8 Original line number Diff line number Diff line Loading @@ -4,17 +4,15 @@ Available on Marvell SOCs: Armada 370 and Armada XP Required properties: - compatible: "marvell,armada-370-xp-pmsu" - compatible: should be "marvell,armada-370-pmsu", whereas "marvell,armada-370-xp-pmsu" is deprecated and will be removed - reg: Should contain PMSU registers location and length. First pair for the per-CPU SW Reset Control registers, second pair for the Power Management Service Unit. - reg: Should contain PMSU registers location and length. Example: armada-370-xp-pmsu@d0022000 { compatible = "marvell,armada-370-xp-pmsu"; reg = <0xd0022100 0x430>, <0xd0020800 0x20>; armada-370-xp-pmsu@22000 { compatible = "marvell,armada-370-pmsu"; reg = <0x22000 0x1000>; };
Documentation/devicetree/bindings/arm/armada-cpu-reset.txt 0 → 100644 +14 −0 Original line number Diff line number Diff line Marvell Armada CPU reset controller =================================== Required properties: - compatible: Should be "marvell,armada-370-cpu-reset". - reg: should be register base and length as documented in the datasheet for the CPU reset registers cpurst: cpurst@20800 { compatible = "marvell,armada-370-cpu-reset"; reg = <0x20800 0x20>; };
arch/arm/mach-mvebu/Makefile +1 −1 Original line number Diff line number Diff line Loading @@ -3,7 +3,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ AFLAGS_coherency_ll.o := -Wa,-march=armv7-a obj-y += system-controller.o mvebu-soc-id.o obj-y += system-controller.o mvebu-soc-id.o cpu-reset.o obj-$(CONFIG_MACH_MVEBU_V7) += board-v7.o obj-$(CONFIG_MACH_DOVE) += dove.o obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o Loading
arch/arm/mach-mvebu/common.h +1 −0 Original line number Diff line number Diff line Loading @@ -18,6 +18,7 @@ #include <linux/reboot.h> void mvebu_restart(enum reboot_mode mode, const char *cmd); int mvebu_cpu_reset_deassert(int cpu); void armada_xp_cpu_die(unsigned int cpu); Loading
arch/arm/mach-mvebu/cpu-reset.c 0 → 100644 +103 −0 Original line number Diff line number Diff line /* * Copyright (C) 2014 Marvell * * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ #define pr_fmt(fmt) "mvebu-cpureset: " fmt #include <linux/kernel.h> #include <linux/init.h> #include <linux/of_address.h> #include <linux/io.h> #include <linux/resource.h> #include "armada-370-xp.h" static void __iomem *cpu_reset_base; static size_t cpu_reset_size; #define CPU_RESET_OFFSET(cpu) (cpu * 0x8) #define CPU_RESET_ASSERT BIT(0) int mvebu_cpu_reset_deassert(int cpu) { u32 reg; if (!cpu_reset_base) return -ENODEV; if (CPU_RESET_OFFSET(cpu) >= cpu_reset_size) return -EINVAL; reg = readl(cpu_reset_base + CPU_RESET_OFFSET(cpu)); reg &= ~CPU_RESET_ASSERT; writel(reg, cpu_reset_base + CPU_RESET_OFFSET(cpu)); return 0; } static int mvebu_cpu_reset_map(struct device_node *np, int res_idx) { struct resource res; if (of_address_to_resource(np, res_idx, &res)) { pr_err("unable to get resource\n"); return -ENOENT; } if (!request_mem_region(res.start, resource_size(&res), np->full_name)) { pr_err("unable to request region\n"); return -EBUSY; } cpu_reset_base = ioremap(res.start, resource_size(&res)); if (!cpu_reset_base) { pr_err("unable to map registers\n"); release_mem_region(res.start, resource_size(&res)); return -ENOMEM; } cpu_reset_size = resource_size(&res); return 0; } int __init mvebu_cpu_reset_init(void) { struct device_node *np; int res_idx; int ret; np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-cpu-reset"); if (np) { res_idx = 0; } else { /* * This code is kept for backward compatibility with * old Device Trees. */ np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-pmsu"); if (np) { pr_warn(FW_WARN "deprecated pmsu binding\n"); res_idx = 1; } } /* No reset node found */ if (!np) return -ENODEV; ret = mvebu_cpu_reset_map(np, res_idx); of_node_put(np); return ret; } early_initcall(mvebu_cpu_reset_init);