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Commit d183c819 authored by Nikita Yushchenko's avatar Nikita Yushchenko Committed by Greg Kroah-Hartman
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fsl-usb: do not test for PHY_CLK_VALID bit on controller version 1.6 



Per reference manuals of Freescale P1020 and P2020 SoCs, USB controller
present in these SoCs has bit 17 of USBx_CONTROL register marked as
Reserved - there is no PHY_CLK_VALID bit there.

Testing for this bit in ehci_fsl_setup_phy() behaves differently on two
P1020RDB boards available here - on one board test passes and fsl-usb
init succeeds, but on other board test fails, causing fsl-usb init to
fail.

This patch changes ehci_fsl_setup_phy() not to test PHY_CLK_VALID on
controller version 1.6 that (per manual) does not have this bit.

Signed-off-by: default avatarNikita Yushchenko <nyushchenko@dev.rtsoft.ru>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent df602c2d

drivers/usb/host/ehci-fsl.c

+2 −1
Original line number Diff line number Diff line
@@ -248,7 +248,8 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, 
		break;

	}



	if (pdata->have_sysif_regs && pdata->controller_ver &&

	if (pdata->have_sysif_regs &&

	    pdata->controller_ver > FSL_USB_VER_1_6 &&

	    (phy_mode == FSL_USB2_PHY_ULPI)) {

		/* check PHY_CLK_VALID to get phy clk valid */

		if (!(spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &