PCI: tegra: Move PCIe driver to drivers/pci/host

NVIDIA Tegra PCIe controller

Required properties:

- compatible: "nvidia,tegra20-pcie"

- device_type: Must be "pci"

- reg: A list of physical base address and length for each set of controller

  registers. Must contain an entry for each entry in the reg-names property.

- reg-names: Must include the following entries:

  "pads": PADS registers

  "afi": AFI registers

  "cs": configuration space region

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

- interrupt-names: Must include the following entries:

  "intr": The Tegra interrupt that is asserted for controller interrupts

  "msi": The Tegra interrupt that is asserted when an MSI is received

- pex-clk-supply: Supply voltage for internal reference clock

- vdd-supply: Power supply for controller (1.05V)

- bus-range: Range of bus numbers associated with this controller

- #address-cells: Address representation for root ports (must be 3)

  - cell 0 specifies the bus and device numbers of the root port:

    [23:16]: bus number

    [15:11]: device number

  - cell 1 denotes the upper 32 address bits and should be 0

  - cell 2 contains the lower 32 address bits and is used to translate to the

    CPU address space

- #size-cells: Size representation for root ports (must be 2)

- ranges: Describes the translation of addresses for root ports and standard

  PCI regions. The entries must be 6 cells each, where the first three cells

  correspond to the address as described for the #address-cells property

  above, the fourth cell is the physical CPU address to translate to and the

  fifth and six cells are as described for the #size-cells property above.

  - The first two entries are expected to translate the addresses for the root

    port registers, which are referenced by the assigned-addresses property of

    the root port nodes (see below).

  - The remaining entries setup the mapping for the standard I/O, memory and

    prefetchable PCI regions. The first cell determines the type of region

    that is setup:

    - 0x81000000: I/O memory region

    - 0x82000000: non-prefetchable memory region

    - 0xc2000000: prefetchable memory region

  Please refer to the standard PCI bus binding document for a more detailed

  explanation.

- clocks: List of clock inputs of the controller. Must contain an entry for

  each entry in the clock-names property.

- clock-names: Must include the following entries:

  "pex": The Tegra clock of that name

  "afi": The Tegra clock of that name

  "pcie_xclk": The Tegra clock of that name

  "pll_e": The Tegra clock of that name

Root ports are defined as subnodes of the PCIe controller node.

Required properties:

- device_type: Must be "pci"

- assigned-addresses: Address and size of the port configuration registers

- reg: PCI bus address of the root port

- #address-cells: Must be 3

- #size-cells: Must be 2

- ranges: Sub-ranges distributed from the PCIe controller node. An empty

  property is sufficient.

- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations

  are:

  - Root port 0 uses 4 lanes, root port 1 is unused.

  - Both root ports use 2 lanes.

Example:

SoC DTSI:

	pcie-controller {

		compatible = "nvidia,tegra20-pcie";

		device_type = "pci";

		reg = <0x80003000 0x00000800   /* PADS registers */

		       0x80003800 0x00000200   /* AFI registers */

		       0x90000000 0x10000000>; /* configuration space */

		reg-names = "pads", "afi", "cs";

		interrupts = <0 98 0x04   /* controller interrupt */

		              0 99 0x04>; /* MSI interrupt */

		interrupt-names = "intr", "msi";

		bus-range = <0x00 0xff>;

		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */

			  0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */

			  0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0xa0000000 0xa0000000 0 0x10000000   /* non-prefetchable memory */

			  0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */

		clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,

			 <&tegra_car 118>;

		clock-names = "pex", "afi", "pcie_xclk", "pll_e";

		status = "disabled";

		pci@1,0 {

			device_type = "pci";

			assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;

			reg = <0x000800 0 0 0 0>;

			status = "disabled";

			#address-cells = <3>;

			#size-cells = <2>;

			ranges;

			nvidia,num-lanes = <2>;

		};

		pci@2,0 {

			device_type = "pci";

			assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;

			reg = <0x001000 0 0 0 0>;

			status = "disabled";

			#address-cells = <3>;

			#size-cells = <2>;

			ranges;

			nvidia,num-lanes = <2>;

		};

	};

Board DTS:

	pcie-controller {

		status = "okay";

		vdd-supply = <&pci_vdd_reg>;

		pex-clk-supply = <&pci_clk_reg>;

		/* root port 00:01.0 */

		pci@1,0 {

			status = "okay";

			/* bridge 01:00.0 (optional) */

			pci@0,0 {

				reg = <0x010000 0 0 0 0>;

				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				/* endpoint 02:00.0 */

				pci@0,0 {

					reg = <0x020000 0 0 0 0>;

				};

			};

		};

	};

Note that devices on the PCI bus are dynamically discovered using PCI's bus

enumeration and therefore don't need corresponding device nodes in DT. However

if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,

device nodes need to be added in order to allow the bus' children to be

instantiated at the proper location in the operating system's device tree (as

illustrated by the optional nodes in the example above).

	select USB_ULPI if USB_PHY

	select USB_ULPI_VIEWPORT if USB_PHY

	select USE_OF

	select MIGHT_HAVE_PCI

	select ARCH_SUPPORTS_MSI

	help

	  This enables support for NVIDIA Tegra based systems.

	  Support for NVIDIA Tegra T114 processor family, based on the

	  ARM CortexA15MP CPU

config TEGRA_PCI

	bool "PCI Express support"

	depends on ARCH_TEGRA_2x_SOC

	select PCI

config TEGRA_AHB

	bool "Enable AHB driver for NVIDIA Tegra SoCs"

	default y

endif

obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o

obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o

obj-$(CONFIG_TEGRA_PCI)			+= pcie.o

obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= tegra114_speedo.o

obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= sleep-tegra30.o

obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= cpuidle-tegra114.o

endif

obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-harmony-pcie.o

obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-paz00.o

/*

 * arch/arm/mach-tegra/board-harmony-pcie.c

 *

 * Copyright (C) 2010 CompuLab, Ltd.

 * Mike Rapoport <mike@compulab.co.il>

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and

 * may be copied, distributed, and modified under those terms.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */

#include <linux/kernel.h>

#include <linux/gpio.h>

#include <linux/err.h>

#include <linux/of_gpio.h>

#include <linux/regulator/consumer.h>

#include <asm/mach-types.h>

#include "board.h"

#ifdef CONFIG_TEGRA_PCI

int __init harmony_pcie_init(void)

{

	struct device_node *np;

	int en_vdd_1v05;

	struct regulator *regulator = NULL;

	int err;

	np = of_find_node_by_path("/regulators/regulator@3");

	if (!np) {

		pr_err("%s: of_find_node_by_path failed\n", __func__);

		return -ENODEV;

	}

	en_vdd_1v05 = of_get_named_gpio(np, "gpio", 0);

	if (en_vdd_1v05 < 0) {

		pr_err("%s: of_get_named_gpio failed: %d\n", __func__,

		       en_vdd_1v05);

		return en_vdd_1v05;

	}

	err = gpio_request(en_vdd_1v05, "EN_VDD_1V05");

	if (err) {

		pr_err("%s: gpio_request failed: %d\n", __func__, err);

		return err;

	}

	gpio_direction_output(en_vdd_1v05, 1);

	regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk");

	if (IS_ERR(regulator)) {

		err = PTR_ERR(regulator);

		pr_err("%s: regulator_get failed: %d\n", __func__, err);

		goto err_reg;

	}

	err = regulator_enable(regulator);

	if (err) {

		pr_err("%s: regulator_enable failed: %d\n", __func__, err);

		goto err_en;

	}

	err = tegra_pcie_init(true, true);

	if (err) {

		pr_err("%s: tegra_pcie_init failed: %d\n", __func__, err);

		goto err_pcie;

	}

	return 0;

err_pcie:

	regulator_disable(regulator);

err_en:

	regulator_put(regulator);

err_reg:

	gpio_free(en_vdd_1v05);

	return err;

}

#endif

void __init tegra_map_common_io(void);

void __init tegra_init_irq(void);

void __init tegra_dt_init_irq(void);

int __init tegra_pcie_init(bool init_port0, bool init_port1);

void tegra_init_late(void);

static inline int tegra_powergate_debugfs_init(void) { return 0; }

#endif

int __init harmony_regulator_init(void);

#ifdef CONFIG_TEGRA_PCI

int __init harmony_pcie_init(void);

#else

static inline int harmony_pcie_init(void) { return 0; }

#endif

void __init tegra_paz00_wifikill_init(void);

#endif