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Commit d11d7e57 authored by Suzuki K. Poulose's avatar Suzuki K. Poulose Committed by Ruchi Kandoi
Browse files

arm64: Track system support for mixed endian EL0 



This patch keeps track of the mixed endian EL0 support across
the system and provides helper functions to export it. The status
is a boolean indicating whether all the CPUs on the system supports
mixed endian at EL0.

Signed-off-by: default avatarSuzuki K. Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Change-Id: Ib2ff964718db4c9175a0ffbf25c7dbb67e2a037a
parent 93f22300

arch/arm64/include/asm/cpufeature.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -26,4 +26,7 @@ static inline bool cpu_have_feature(unsigned int num) 
	return elf_hwcap & (1UL << num);

	return elf_hwcap & (1UL << num);

}

}





bool cpu_supports_mixed_endian_el0(void);

bool system_supports_mixed_endian_el0(void);



#endif
 
#endif

arch/arm64/include/asm/cputype.h

+14 −0
Original line number Original line Diff line number Diff line
@@ -67,6 +67,15 @@ 




#define APM_CPU_PART_POTENZA	0x000

#define APM_CPU_PART_POTENZA	0x000





#define ID_AA64MMFR0_BIGENDEL0_SHIFT	16

#define ID_AA64MMFR0_BIGENDEL0_MASK	(0xf << ID_AA64MMFR0_BIGENDEL0_SHIFT)

#define ID_AA64MMFR0_BIGENDEL0(mmfr0)	\

	(((mmfr0) & ID_AA64MMFR0_BIGENDEL0_MASK) >> ID_AA64MMFR0_BIGENDEL0_SHIFT)

#define ID_AA64MMFR0_BIGEND_SHIFT	8

#define ID_AA64MMFR0_BIGEND_MASK	(0xf << ID_AA64MMFR0_BIGEND_SHIFT)

#define ID_AA64MMFR0_BIGEND(mmfr0)	\

	(((mmfr0) & ID_AA64MMFR0_BIGEND_MASK) >> ID_AA64MMFR0_BIGEND_SHIFT)



#ifndef __ASSEMBLY__

#ifndef __ASSEMBLY__





/*

/*
@@ -99,6 +108,11 @@ static inline u32 __attribute_const__ read_cpuid_cachetype(void) 
	return read_cpuid(CTR_EL0);

	return read_cpuid(CTR_EL0);

}

}





static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)

{

	return (ID_AA64MMFR0_BIGEND(mmfr0) == 0x1) ||

		(ID_AA64MMFR0_BIGENDEL0(mmfr0) == 0x1);

}

#endif /* __ASSEMBLY__ */

#endif /* __ASSEMBLY__ */





#endif
 
#endif

arch/arm64/kernel/cpuinfo.c

+22 −0
Original line number Original line Diff line number Diff line
@@ -34,6 +34,27 @@ 
 */

 */

DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);

DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);

static struct cpuinfo_arm64 boot_cpu_data;

static struct cpuinfo_arm64 boot_cpu_data;

static bool mixed_endian_el0 = true;



bool cpu_supports_mixed_endian_el0(void)

{

	return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));

}



bool system_supports_mixed_endian_el0(void)

{

	return mixed_endian_el0;

}



static void update_mixed_endian_el0_support(struct cpuinfo_arm64 *info)

{

	mixed_endian_el0 &= id_aa64mmfr0_mixed_endian_el0(info->reg_id_aa64mmfr0);

}



static void update_cpu_features(struct cpuinfo_arm64 *info)

{

	update_mixed_endian_el0_support(info);

}





static char *icache_policy_str[] = {

static char *icache_policy_str[] = {

	[ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",

	[ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
@@ -186,6 +207,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 
	info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);

	info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);





	cpuinfo_detect_icache_policy(info);

	cpuinfo_detect_icache_policy(info);

	update_cpu_features(info);

}

}





void cpuinfo_store_cpu(void)

void cpuinfo_store_cpu(void)