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Commit d0c8db08 authored by Kiran Gunda's avatar Kiran Gunda
Browse files

ARM: dts: msm: configure I2C node for msmgold 



Configure BLSP1QUP2, BLSP1QUP3 and BLSP2QUP1
in i2c mode to enable communication with the
i2c slave devices.

Change-Id: Ibc49926f906d90cbd93c8bc8adc91046cd75dae3
Signed-off-by: default avatarKiran Gunda <kgunda@codeaurora.org>
parent 1c2c6d7f

arch/arm/boot/dts/qcom/msmgold-pinctrl.dtsi

+91 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -654,5 +654,95 @@ 
				};

			};

		};



		i2c_2 {

			i2c_2_active: i2c_2_active {

				/* active state */

				mux {

					pins = "gpio6", "gpio7";

					function = "blsp_i2c2";

				};



				config {

					pins = "gpio6", "gpio7";

					drive-strength = <2>;

					bias-disable;

				};

			};



			i2c_2_sleep: i2c_2_sleep {

				/* suspended state */

				mux {

					pins = "gpio6", "gpio7";

					function = "gpio";

				};



				config {

					pins = "gpio6", "gpio7";

					drive-strength = <2>;

					bias-pull-down;

				};

			};

		};



		i2c_3 {

			i2c_3_active: i2c_3_active {

				/* active state */

				mux {

					pins = "gpio10", "gpio11";

					function = "blsp_i2c3";

				};



				config {

					pins = "gpio10", "gpio11";

					drive-strength = <2>;

					bias-disable;

				};

			};



			i2c_3_sleep: i2c_3_sleep {

				/* suspended state */

				mux {

					pins = "gpio10", "gpio11";

					function = "gpio";

				};



				config {

					pins = "gpio10", "gpio11";

					drive-strength = <2>;

					bias-pull-down;

				};

			};

		};



		i2c_5 {

			i2c_5_active: i2c_5_active {

				/* active state */

				mux {

					pins = "gpio18", "gpio19";

					function = "blsp_i2c5";

				};



				config {

					pins = "gpio18", "gpio19";

					drive-strength = <2>;

					bias-disable;

				};

			};



			i2c_5_sleep: i2c_5_sleep {

				/* suspended state */

				mux {

					pins = "gpio18", "gpio19";

					function = "gpio";

				};



				config {

					pins = "gpio18", "gpio19";

					drive-strength = <2>;

					bias-pull-down;

				};

			};

		};

	};

};

arch/arm/boot/dts/qcom/msmgold.dtsi

+96 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -36,6 +36,9 @@ 
		smd21 = &smdtty_data21;

		smd36 = &smdtty_loopback;

		spi3 = &spi_3;

		i2c2 = &i2c_2;

		i2c5 = &i2c_5;

		i2c3 = &i2c_3;

	};



	reserved-memory {
@@ -428,6 +431,98 @@ 
		clock-names = "core_clk", "iface_clk";

	};



	dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */

		#dma-cells = <4>;

		compatible = "qcom,sps-dma";

		reg = <0x7884000 0x1f000>;

		interrupts = <0 238 0>;

		qcom,summing-threshold = <10>;

	};



	dma_blsp2: qcom,sps-dma@7ac4000 { /* BLSP2 */

		#dma-cells = <4>;

		compatible = "qcom,sps-dma";

		reg = <0x7ac4000 0x1f000>;

		interrupts = <0 239 0>;

		qcom,summing-threshold = <10>;

	};



	i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */

		compatible = "qcom,i2c-msm-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "qup_phys_addr";

		reg = <0x78b6000 0x600>;

		interrupt-names = "qup_irq";

		interrupts = <0 96 0>;

		qcom,clk-freq-out = <400000>;

		qcom,clk-freq-in  = <19200000>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			<&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;



		pinctrl-names = "i2c_active", "i2c_sleep";

		pinctrl-0 = <&i2c_2_active>;

		pinctrl-1 = <&i2c_2_sleep>;

		qcom,noise-rjct-scl = <0>;

		qcom,noise-rjct-sda = <0>;

		qcom,master-id = <86>;

		dmas = <&dma_blsp1 6 64 0x20000020 0x20>,

			<&dma_blsp1 7 32 0x20000020 0x20>;

		dma-names = "tx", "rx";

	};



	i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */

		compatible = "qcom,i2c-msm-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "qup_phys_addr";

		reg = <0x78b7000 0x600>;

		interrupt-names = "qup_irq";

		interrupts = <0 97 0>;

		qcom,clk-freq-out = <400000>;

		qcom,clk-freq-in  = <19200000>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			<&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>;



		pinctrl-names = "i2c_active", "i2c_sleep";

		pinctrl-0 = <&i2c_3_active>;

		pinctrl-1 = <&i2c_3_sleep>;

		qcom,noise-rjct-scl = <0>;

		qcom,noise-rjct-sda = <0>;

		qcom,master-id = <86>;

		dmas = <&dma_blsp1 8 64 0x20000020 0x20>,

			<&dma_blsp1 9 32 0x20000020 0x20>;

		dma-names = "tx", "rx";

		status = "disabled";

	};



	i2c_5: i2c@7af5000 { /* BLSP2 QUP1 */

		compatible = "qcom,i2c-msm-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "qup_phys_addr";

		reg = <0x7af5000 0x600>;

		interrupt-names = "qup_irq";

		interrupts = <0 299 0>;

		qcom,clk-freq-out = <400000>;

		qcom,clk-freq-in  = <19200000>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,

			<&clock_gcc clk_gcc_blsp2_qup1_i2c_apps_clk>;



		pinctrl-names = "i2c_active", "i2c_sleep";

		pinctrl-0 = <&i2c_5_active>;

		pinctrl-1 = <&i2c_5_sleep>;

		qcom,noise-rjct-scl = <0>;

		qcom,noise-rjct-sda = <0>;

		qcom,master-id = <84>;

		dmas = <&dma_blsp2 4 64 0x20000020 0x20>,

			<&dma_blsp2 5 32 0x20000020 0x20>;

		dma-names = "tx", "rx";

	};



	rpm_bus: qcom,rpm-smd {

		compatible = "qcom,rpm-smd";

		rpm-channel-name = "rpm_requests";