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Commit d0c82aa0 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: msm: clock-gcc: Add support for bimc gpu clock"

parents 8aaaf9db e7b9e0c5
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+14 −0
Original line number Diff line number Diff line
@@ -1954,6 +1954,17 @@ static struct branch_clk gcc_blsp2_uart2_apps_clk = {
	},
};

static struct branch_clk gcc_bimc_gpu_clk = {
	.cbcr_reg = BIMC_GPU_CBCR,
	.has_sibling = 1,
	.base = &virt_bases[GCC_BASE],
	.c = {
		.dbg_name = "gcc_bimc_gpu_clk",
		.ops = &clk_ops_branch,
		CLK_INIT(gcc_bimc_gpu_clk.c),
	},
};

static struct branch_clk gcc_camss_cci_ahb_clk = {
	.cbcr_reg = CAMSS_CCI_AHB_CBCR,
	.has_sibling = 1,
@@ -3131,6 +3142,7 @@ static struct local_vote_clk gcc_crypto_clk = {
	.base = &virt_bases[GCC_BASE],
	.c = {
		.dbg_name = "gcc_crypto_clk",
		.parent = &crypto_clk_src.c,
		.ops = &clk_ops_vote,
		CLK_INIT(gcc_crypto_clk.c),
	},
@@ -3383,6 +3395,7 @@ static struct mux_clk gcc_debug_mux = {
		{ &gcc_crypto_clk.c, 0x0138 },
		{ &gcc_crypto_axi_clk.c, 0x0139 },
		{ &gcc_crypto_ahb_clk.c, 0x013a },
		{ &gcc_bimc_gpu_clk.c, 0x0157 },
		{ &gcc_apss_ahb_clk.c, 0x0168 },
		{ &gcc_apss_axi_clk.c, 0x0169 },
		{ &gcc_vfe1_tbu_clk.c, 0x0199 },
@@ -3909,6 +3922,7 @@ static struct clk_lookup msm_clocks_gcc_gfx[] = {
	CLK_LIST(gcc_oxili_gfx3d_clk),
	CLK_LIST(gcc_oxili_timer_clk),
	CLK_LIST(gcc_bimc_gfx_clk),
	CLK_LIST(gcc_bimc_gpu_clk),
};

static int of_get_fmax_vdd_class(struct platform_device *pdev, struct clk *c,
+1 −0
Original line number Diff line number Diff line
@@ -455,6 +455,7 @@
#define GFX3D_CFG_RCGR					0x59004
#define OXILI_GFX3D_CBCR				0x59020
#define OXILI_AHB_CBCR					0x59028
#define BIMC_GPU_CBCR					0x59030
#define OXILI_TIMER_CBCR				0x59040
#define CAMSS_TOP_AHB_CMD_RCGR				0x5A000
#define CAMSS_TOP_AHB_CFG_RCGR				0x5A004
+1 −0
Original line number Diff line number Diff line
@@ -244,6 +244,7 @@
#define clk_gcc_mss_cfg_ahb_clk				 0x111cde81
#define clk_gcc_mss_q6_bimc_axi_clk			 0x67544d62
#define clk_gcc_bimc_gfx_clk				 0x3edd69ad
#define clk_gcc_bimc_gpu_clk				 0x19922503
#define clk_gcc_oxili_ahb_clk				 0xd15c8a00
#define clk_gcc_oxili_aon_clk				 0xae18e54d
#define clk_gcc_oxili_gfx3d_clk				 0x49a51fd9