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Commit d090ddda authored by Hyok S. Choi's avatar Hyok S. Choi Committed by Russell King
Browse files

[ARM] nommu: Initial uCLinux support for MMU-based CPUs 



In noMMU mode, various of functions which are defined in mm/proc-*.S
is not valid or needed to be avoided. i.g. switch_mm is not needed,
just returns and this makes the I & D caches are valid which shows
great improvement of performance including task switching and IPC.

Signed-off-by: default avatarHyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent a4f7e763

arch/arm/mm/proc-arm1020.S

+9 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 *

 *  Copyright (C) 2000 ARM Limited

 *  Copyright (C) 2000 Deep Blue Solutions Ltd.

 *  hacked for non-paged-MM by Hyok S. Choi, 2003.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by
@@ -101,7 +102,9 @@ ENTRY(cpu_arm1020_reset) 
	mov	ip, #0

	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches

	mcr	p15, 0, ip, c7, c10, 4		@ drain WB

#ifdef CONFIG_MMU

	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs

#endif

	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register

	bic	ip, ip, #0x000f 		@ ............wcam

	bic	ip, ip, #0x1100 		@ ...i...s........
@@ -359,6 +362,7 @@ ENTRY(cpu_arm1020_dcache_clean_area) 
 */

	.align	5

ENTRY(cpu_arm1020_switch_mm)

#ifdef CONFIG_MMU

#ifndef CONFIG_CPU_DCACHE_DISABLE

	mcr	p15, 0, r3, c7, c10, 4

	mov	r1, #0xF			@ 16 segments
@@ -383,6 +387,7 @@ ENTRY(cpu_arm1020_switch_mm) 
	mcr	p15, 0, r1, c7, c10, 4		@ drain WB

	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer

	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs

#endif /* CONFIG_MMU */

	mov	pc, lr

        

/*
@@ -392,6 +397,7 @@ ENTRY(cpu_arm1020_switch_mm) 
 */

	.align	5

ENTRY(cpu_arm1020_set_pte)

#ifdef CONFIG_MMU

	str	r1, [r0], #-2048		@ linux version



	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -421,6 +427,7 @@ ENTRY(cpu_arm1020_set_pte) 
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry

#endif

	mcr	p15, 0, r0, c7, c10, 4		@ drain WB

#endif /* CONFIG_MMU */

	mov	pc, lr



	__INIT
@@ -430,7 +437,9 @@ __arm1020_setup: 
	mov	r0, #0

	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4

	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4

#ifdef CONFIG_MMU

	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4

#endif

	mrc	p15, 0, r0, c1, c0		@ get control register v4

	ldr	r5, arm1020_cr1_clear

	bic	r0, r0, r5

arch/arm/mm/proc-arm1020e.S

+9 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 *

 *  Copyright (C) 2000 ARM Limited

 *  Copyright (C) 2000 Deep Blue Solutions Ltd.

 *  hacked for non-paged-MM by Hyok S. Choi, 2003.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by
@@ -101,7 +102,9 @@ ENTRY(cpu_arm1020e_reset) 
	mov	ip, #0

	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches

	mcr	p15, 0, ip, c7, c10, 4		@ drain WB

#ifdef CONFIG_MMU

	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs

#endif

	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register

	bic	ip, ip, #0x000f 		@ ............wcam

	bic	ip, ip, #0x1100 		@ ...i...s........
@@ -344,6 +347,7 @@ ENTRY(cpu_arm1020e_dcache_clean_area) 
 */

	.align	5

ENTRY(cpu_arm1020e_switch_mm)

#ifdef CONFIG_MMU

#ifndef CONFIG_CPU_DCACHE_DISABLE

	mcr	p15, 0, r3, c7, c10, 4

	mov	r1, #0xF			@ 16 segments
@@ -367,6 +371,7 @@ ENTRY(cpu_arm1020e_switch_mm) 
	mcr	p15, 0, r1, c7, c10, 4		@ drain WB

	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer

	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs

#endif

	mov	pc, lr

        

/*
@@ -376,6 +381,7 @@ ENTRY(cpu_arm1020e_switch_mm) 
 */

	.align	5

ENTRY(cpu_arm1020e_set_pte)

#ifdef CONFIG_MMU

	str	r1, [r0], #-2048		@ linux version



	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -403,6 +409,7 @@ ENTRY(cpu_arm1020e_set_pte) 
#ifndef CONFIG_CPU_DCACHE_DISABLE

	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry

#endif

#endif /* CONFIG_MMU */

	mov	pc, lr



	__INIT
@@ -412,7 +419,9 @@ __arm1020e_setup: 
	mov	r0, #0

	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4

	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4

#ifdef CONFIG_MMU

	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4

#endif

	mrc	p15, 0, r0, c1, c0		@ get control register v4

	ldr	r5, arm1020e_cr1_clear

	bic	r0, r0, r5

arch/arm/mm/proc-arm1022.S

+9 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 *

 *  Copyright (C) 2000 ARM Limited

 *  Copyright (C) 2000 Deep Blue Solutions Ltd.

 *  hacked for non-paged-MM by Hyok S. Choi, 2003.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by
@@ -90,7 +91,9 @@ ENTRY(cpu_arm1022_reset) 
	mov	ip, #0

	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches

	mcr	p15, 0, ip, c7, c10, 4		@ drain WB

#ifdef CONFIG_MMU

	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs

#endif

	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register

	bic	ip, ip, #0x000f 		@ ............wcam

	bic	ip, ip, #0x1100 		@ ...i...s........
@@ -333,6 +336,7 @@ ENTRY(cpu_arm1022_dcache_clean_area) 
 */

	.align	5

ENTRY(cpu_arm1022_switch_mm)

#ifdef CONFIG_MMU

#ifndef CONFIG_CPU_DCACHE_DISABLE

	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 16 segments

1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
@@ -349,6 +353,7 @@ ENTRY(cpu_arm1022_switch_mm) 
	mcr	p15, 0, r1, c7, c10, 4		@ drain WB

	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer

	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs

#endif

	mov	pc, lr

        

/*
@@ -358,6 +363,7 @@ ENTRY(cpu_arm1022_switch_mm) 
 */

	.align	5

ENTRY(cpu_arm1022_set_pte)

#ifdef CONFIG_MMU

	str	r1, [r0], #-2048		@ linux version



	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -385,6 +391,7 @@ ENTRY(cpu_arm1022_set_pte) 
#ifndef CONFIG_CPU_DCACHE_DISABLE

	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry

#endif

#endif /* CONFIG_MMU */

	mov	pc, lr



	__INIT
@@ -394,7 +401,9 @@ __arm1022_setup: 
	mov	r0, #0

	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4

	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4

#ifdef CONFIG_MMU

	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4

#endif

	mrc	p15, 0, r0, c1, c0		@ get control register v4

	ldr	r5, arm1022_cr1_clear

	bic	r0, r0, r5

arch/arm/mm/proc-arm1026.S

+9 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 *

 *  Copyright (C) 2000 ARM Limited

 *  Copyright (C) 2000 Deep Blue Solutions Ltd.

 *  hacked for non-paged-MM by Hyok S. Choi, 2003.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by
@@ -90,7 +91,9 @@ ENTRY(cpu_arm1026_reset) 
	mov	ip, #0

	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches

	mcr	p15, 0, ip, c7, c10, 4		@ drain WB

#ifdef CONFIG_MMU

	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs

#endif

	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register

	bic	ip, ip, #0x000f 		@ ............wcam

	bic	ip, ip, #0x1100 		@ ...i...s........
@@ -327,6 +330,7 @@ ENTRY(cpu_arm1026_dcache_clean_area) 
 */

	.align	5

ENTRY(cpu_arm1026_switch_mm)

#ifdef CONFIG_MMU

	mov	r1, #0

#ifndef CONFIG_CPU_DCACHE_DISABLE

1:	mrc	p15, 0, r15, c7, c14, 3		@ test, clean, invalidate
@@ -338,6 +342,7 @@ ENTRY(cpu_arm1026_switch_mm) 
	mcr	p15, 0, r1, c7, c10, 4		@ drain WB

	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer

	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs

#endif

	mov	pc, lr

        

/*
@@ -347,6 +352,7 @@ ENTRY(cpu_arm1026_switch_mm) 
 */

	.align	5

ENTRY(cpu_arm1026_set_pte)

#ifdef CONFIG_MMU

	str	r1, [r0], #-2048		@ linux version



	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -374,6 +380,7 @@ ENTRY(cpu_arm1026_set_pte) 
#ifndef CONFIG_CPU_DCACHE_DISABLE

	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry

#endif

#endif /* CONFIG_MMU */

	mov	pc, lr
@@ -384,8 +391,10 @@ __arm1026_setup: 
	mov	r0, #0

	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4

	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4

#ifdef CONFIG_MMU

	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4

	mcr	p15, 0, r4, c2, c0		@ load page table pointer

#endif

#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

	mov	r0, #4				@ explicitly disable writeback

	mcr	p15, 7, r0, c15, c0, 0

arch/arm/mm/proc-arm6_7.S

+15 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
 *  linux/arch/arm/mm/proc-arm6,7.S

 *

 *  Copyright (C) 1997-2000 Russell King

 *  hacked for non-paged-MM by Hyok S. Choi, 2003.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as
@@ -199,10 +200,12 @@ ENTRY(cpu_arm7_do_idle) 
 */

ENTRY(cpu_arm6_switch_mm)

ENTRY(cpu_arm7_switch_mm)

#ifdef CONFIG_MMU

		mov	r1, #0

		mcr	p15, 0, r1, c7, c0, 0		@ flush cache

		mcr	p15, 0, r0, c2, c0, 0		@ update page table ptr

		mcr	p15, 0, r1, c5, c0, 0		@ flush TLBs

#endif

		mov	pc, lr



/*
@@ -214,6 +217,7 @@ ENTRY(cpu_arm7_switch_mm) 
		.align	5

ENTRY(cpu_arm6_set_pte)

ENTRY(cpu_arm7_set_pte)

#ifdef CONFIG_MMU

		str	r1, [r0], #-2048		@ linux version



		eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -232,6 +236,7 @@ ENTRY(cpu_arm7_set_pte) 
		movne	r2, #0



		str	r2, [r0]			@ hardware version

#endif /* CONFIG_MMU */

		mov	pc, lr



/*
@@ -243,7 +248,9 @@ ENTRY(cpu_arm6_reset) 
ENTRY(cpu_arm7_reset)

		mov	r1, #0

		mcr	p15, 0, r1, c7, c0, 0		@ flush cache

#ifdef CONFIG_MMU

		mcr	p15, 0, r1, c5, c0, 0		@ flush TLB

#endif

		mov	r1, #0x30

		mcr	p15, 0, r1, c1, c0, 0		@ turn off MMU etc

		mov	pc, r0
@@ -253,19 +260,27 @@ ENTRY(cpu_arm7_reset) 
		.type	__arm6_setup, #function

__arm6_setup:	mov	r0, #0

		mcr	p15, 0, r0, c7, c0		@ flush caches on v3

#ifdef CONFIG_MMU

		mcr	p15, 0, r0, c5, c0		@ flush TLBs on v3

		mov	r0, #0x3d			@ . ..RS BLDP WCAM

		orr	r0, r0, #0x100			@ . ..01 0011 1101

#else

		mov	r0, #0x3c			@ . ..RS BLDP WCA.

#endif

		mov	pc, lr

		.size	__arm6_setup, . - __arm6_setup



		.type	__arm7_setup, #function

__arm7_setup:	mov	r0, #0

		mcr	p15, 0, r0, c7, c0		@ flush caches on v3

#ifdef CONFIG_MMU

		mcr	p15, 0, r0, c5, c0		@ flush TLBs on v3

		mcr	p15, 0, r0, c3, c0		@ load domain access register

		mov	r0, #0x7d			@ . ..RS BLDP WCAM

		orr	r0, r0, #0x100			@ . ..01 0111 1101

#else

		mov	r0, #0x7c			@ . ..RS BLDP WCA.

#endif

		mov	pc, lr

		.size	__arm7_setup, . - __arm7_setup