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Commit d03d1818 authored by Patrick Daly's avatar Patrick Daly
Browse files

ARM: dts: msm: Add coresight etm support for mdmcalifornium 



Add the CoreSight sources, sinks, and interconnect components necessary for
apps etm tracing.

Change-Id: If8aa9fb0405ce56e541f4f70e8ec8b55ed493318
Signed-off-by: default avatarPatrick Daly <pdaly@codeaurora.org>
parent d9479b68

arch/arm/boot/dts/qcom/mdmcalifornium-coresight.dtsi

0 → 100644
+190 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	tmc_etr: tmc@828000 {

		compatible = "arm,coresight-tmc";

		reg = <0x828000 0x1000>,

		      <0x884000 0x15000>;

		reg-names = "tmc-base", "bam-base";

		interrupts = <0 166 0>;

		interrupt-names = "byte-cntr-irq";



		qcom,memory-size = <0x100000>;

		qcom,sg-enable;



		coresight-id = <1>;

		coresight-name = "coresight-tmc-etr";

		coresight-nr-inports = <1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	replicator: replicator@3026000 {

		compatible = "qcom,coresight-replicator";

		reg = <0x826000 0x1000>;

		reg-names = "replicator-base";



		coresight-id = <2>;

		coresight-name = "coresight-replicator";

		coresight-nr-inports = <1>;

		coresight-outports = <0>;

		coresight-child-list = <&tmc_etr>;

		coresight-child-ports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	tmc_etf: tmc@827000 {

		compatible = "arm,coresight-tmc";

		reg = <0x827000 0x1000>;

		reg-names = "tmc-base";



		coresight-id = <3>;

		coresight-name = "coresight-tmc-etf";

		coresight-nr-inports = <1>;

		coresight-outports = <0>;

		coresight-child-list = <&replicator>;

		coresight-child-ports = <0>;

		coresight-default-sink;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	funnel_merge: funnel@825000 {

		compatible = "arm,coresight-funnel";

		reg = <0x825000 0x1000>;

		reg-names = "funnel-base";



		coresight-id = <4>;

		coresight-name = "coresight-funnel-merg";

		coresight-nr-inports = <2>;

		coresight-outports = <0>;

		coresight-child-list = <&tmc_etf>;

		coresight-child-ports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	funnel_in0: funnel@821000 {

		compatible = "arm,coresight-funnel";

		reg = <0x821000 0x1000>;

		reg-names = "funnel-base";



		coresight-id = <5>;

		coresight-name = "coresight-funnel-in0";

		coresight-nr-inports = <8>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_merge>;

		coresight-child-ports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	funnel_in1: funnel@822000 {

		compatible = "arm,coresight-funnel";

		reg = <0x822000 0x1000>;

		reg-names = "funnel-base";



		coresight-id = <6>;

		coresight-name = "coresight-funnel-in1";

		coresight-nr-inports = <8>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_merge>;

		coresight-child-ports = <1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	modem_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-id = <7>;

		coresight-name = "coresight-modem-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in1>;

		coresight-child-ports = <6>;



		qcom,inst-id = <2>;

	};



	rpm_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-id = <8>;

		coresight-name = "coresight-rpm-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <0>;



		qcom,inst-id = <4>;

	};



	etm0: etm@842000 {

		compatible = "arm,coresight-etm";

		reg = <0x842000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <9>;

		coresight-name = "coresight-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in1>;

		coresight-child-ports = <7>;

		coresight-etm-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	fuse: fuse@a601c {

		compatible = "arm,coresight-fuse-v2";

		reg = <0xa601c 0x8>,

		      <0xa600c 0x4>;

		reg-names = "fuse-base", "qpdi-fuse-base";



		coresight-id = <10>;

		coresight-name = "coresight-fuse";

		coresight-nr-inports = <0>;

	};



	csr: csr@801000 {

		compatible = "qcom,coresight-csr";

		reg = <0x801000 0x1000>;

		reg-names = "csr-base";



		coresight-id = <11>;

		coresight-name = "coresight-csr";

		coresight-nr-inports = <0>;



		qcom,blk-size = <1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};

};

arch/arm/boot/dts/qcom/mdmcalifornium.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -69,6 +69,7 @@ 
#include "msm-gdsc.dtsi"

#include "mdmcalifornium-blsp.dtsi"

#include "mdmcalifornium-bus.dtsi"

#include "mdmcalifornium-coresight.dtsi"



&soc {

	#address-cells = <1>;