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Commit cfc52eb6 authored by Alan Cox's avatar Alan Cox Committed by Greg Kroah-Hartman
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Staging: et131x: Another typedef solely used to write 0 to a register

parent 42a03e98
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+5 −15
Original line number Diff line number Diff line
@@ -803,21 +803,11 @@ typedef union _TXMAC_ERR_INT_t {
/*
 * structure for error interrupt reg in txmac address map
 * located at address 0x3020
 *
 * 31-2: unused
 * 1: bp_req
 * 0: bp_xonxoff
 */
typedef union _TXMAC_CP_CTRL_t {
	u32 value;
	struct {
#ifdef _BIT_FIELDS_HTOL
		u32 unused:30;		/* bits 2-31 */
		u32 bp_req:1;		/* bit 1 */
		u32 bp_xonxoff:1;	/* bit 0 */
#else
		u32 bp_xonxoff:1;	/* bit 0 */
		u32 bp_req:1;		/* bit 1 */
		u32 unused:30;		/* bits 2-31 */
#endif
	} bits;
} TXMAC_BP_CTRL_t, *PTXMAC_BP_CTRL_t;

/*
 * Tx MAC Module of JAGCore Address Mapping
@@ -831,7 +821,7 @@ typedef struct _TXMAC_t { /* Location: */
	u32 tx_test;			/*  0x3014 */
	TXMAC_ERR_t err;		/*  0x3018 */
	TXMAC_ERR_INT_t err_int;	/*  0x301C */
	TXMAC_BP_CTRL_t bp_ctrl;	/*  0x3020 */
	u32 bp_ctrl;			/*  0x3020 */
} TXMAC_t, *PTXMAC_t;

/* END OF TXMAC REGISTER ADDRESS MAP */
+4 −9
Original line number Diff line number Diff line
@@ -287,17 +287,12 @@ void et131x_isr_handler(struct work_struct *work)
				u32 pm_csr;

				/* Tell the device to send a pause packet via
				 * the back pressure register
				 * the back pressure register (bp req  and
				 * bp xon/xoff)
				 */
				pm_csr = readl(&iomem->global.pm_csr);
				if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
					TXMAC_BP_CTRL_t bp_ctrl = { 0 };

					bp_ctrl.bits.bp_req = 1;
					bp_ctrl.bits.bp_xonxoff = 1;
					writel(bp_ctrl.value,
					       &iomem->txmac.bp_ctrl.value);
				}
				if ((pm_csr & ET_PM_PHY_SW_COMA) == 0)
					writel(3, &iomem->txmac.bp_ctrl);
			}
		}