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Commit cfbc8328 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable the GPU clock driver on MSMCOBALT"

parents 073b4b47 f3c17935

arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi

+6 −1
Original line number Original line Diff line number Diff line 
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.

 *

 *

 * This program is free software; you can redistribute it and/or modify

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * it under the terms of the GNU General Public License version 2 and
@@ -55,6 +55,11 @@ 
	#clock-cells = <1>;

	#clock-cells = <1>;

};

};





&clock_gpu {

	compatible = "qcom,dummycc";

	#clock-cells = <1>;

};



&soc {

&soc {

	qcom,icnss@18800000 {

	qcom,icnss@18800000 {

	compatible = "qcom,icnss";

	compatible = "qcom,icnss";

arch/arm/boot/dts/qcom/msmcobalt.dtsi

+28 −1
Original line number Original line Diff line number Diff line
@@ -327,7 +327,32 @@ 
	};

	};





	clock_gpu: qcom,gpucc@5065000 {

	clock_gpu: qcom,gpucc@5065000 {

		compatible = "qcom,dummycc";

		compatible = "qcom,gpucc-cobalt";

		reg = <0x5065000 0x9000>;

		reg-names = "cc_base";

		vdd_gpucc-supply = <&pm8005_s1>;

		vdd_dig-supply = <&pmcobalt_s1_level>;

		vdd_mx-supply = <&pmcobalt_s9_level>;

		vdd_gpu_mx-supply = <&pmcobalt_s9_level>;

		clock-names = "xo", "gpll0";

		clocks = <&clock_gcc clk_cxo_clk_src>,

			<&clock_gcc clk_gpll0_out_main>;

		qcom,gfxfreq-speedbin0 =

			<	  0	 0			     0 >,

			< 171000000 520000 RPM_SMD_REGULATOR_LEVEL_SVS >,

			< 251000000 570000 RPM_SMD_REGULATOR_LEVEL_SVS >,

			< 332000000 630000 RPM_SMD_REGULATOR_LEVEL_SVS >,

			< 403000000 680000 RPM_SMD_REGULATOR_LEVEL_SVS >,

			< 504000000 745000 RPM_SMD_REGULATOR_LEVEL_NOM >,

			< 650000000 855000 RPM_SMD_REGULATOR_LEVEL_TURBO >;

		qcom,gfxfreq-mx-speedbin0 =

			<         0			      0 >,

			< 171000000 RPM_SMD_REGULATOR_LEVEL_SVS >,

			< 251000000 RPM_SMD_REGULATOR_LEVEL_SVS >,

			< 332000000 RPM_SMD_REGULATOR_LEVEL_SVS >,

			< 403000000 RPM_SMD_REGULATOR_LEVEL_SVS >,

			< 504000000 RPM_SMD_REGULATOR_LEVEL_NOM >,

			< 650000000 RPM_SMD_REGULATOR_LEVEL_TURBO >;

		#clock-cells = <1>;

		#clock-cells = <1>;

	};

	};
@@ -335,6 +360,8 @@ 
		compatible = "qcom,cc-debug-cobalt";

		compatible = "qcom,cc-debug-cobalt";

		reg = <0x162000 0x4>;

		reg = <0x162000 0x4>;

		reg-names = "cc_base";

		reg-names = "cc_base";

		clock-names = "debug_gpu_clk";

		clocks = <&clock_gpu clk_gpucc_gcc_dbg_clk>;

		#clock-cells = <1>;

		#clock-cells = <1>;

	};

	};