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Commit cf757899 authored by Chris Dearman's avatar Chris Dearman Committed by Ralf Baechle
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[MIPS] SMTC: Fix build error caused by nonsense code. 



Signed-off-by: default avatarChris Dearman <chris@mips.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 6a05888d

arch/mips/mips-boards/generic/time.c

+2 −14
Original line number Diff line number Diff line
@@ -88,8 +88,6 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id) 
	 *  the general MIPS timer_interrupt routine.

	 */



	int vpflags;



	/*

	 * We could be here due to timer interrupt,

	 * perf counter overflow, or both.
@@ -98,15 +96,6 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id) 
		perf_irq();



	if (read_c0_cause() & (1 << 30)) {

		/* If timer interrupt, make it de-assert */

		write_c0_compare (read_c0_count() - 1);

		/*

		 * DVPE is necessary so long as cross-VPE interrupts

		 * are done via read-modify-write of Cause register.

		 */

		vpflags = dvpe();

		clear_c0_cause(CPUCTR_IMASKBIT);

		evpe(vpflags);

		/*

		 * There are things we only want to do once per tick

		 * in an "MP" system.   One TC of each VPE will take
@@ -116,13 +105,12 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id) 
		 */

		if (cpu_data[cpu].vpe_id == 0) {

			timer_interrupt(irq, NULL);

				smtc_timer_broadcast(cpu_data[cpu].vpe_id);

		} else {

			write_c0_compare(read_c0_count() +

			                 (mips_hpt_frequency/HZ));

			local_timer_interrupt(irq, dev_id);

			smtc_timer_broadcast(cpu_data[cpu].vpe_id);

		}

		smtc_timer_broadcast(cpu_data[cpu].vpe_id);

	}

#else /* CONFIG_MIPS_MT_SMTC */

	int r2 = cpu_has_mips_r2;