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Commit cec907e0 authored by Sandeep Panda's avatar Sandeep Panda
Browse files

ARM: dts: msm: update reference to msm8937 dsi pll clocks 



Latest DSI 28nm HPM PHY driver has support for two
independent DSI PLL. Update the reference to DSI PLL clocks
in msm8937 device tree based on latest DSI PHY driver.

Change-Id: I11d2774124ecb2d0743b098db2ce3a01be71440b
Signed-off-by: default avatarSandeep Panda <spanda@codeaurora.org>
parent 58be1b1f

arch/arm/boot/dts/qcom/msm8937-mdss-pll.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -53,7 +53,6 @@ 
	};



	mdss_dsi1_pll: qcom,mdss_dsi_pll@1a96a00 {

		status = "disabled";

		compatible = "qcom,mdss_dsi_pll_8937";

		label = "MDSS DSI 1 PLL";

		cell-index = <1>;

arch/arm/boot/dts/qcom/msm8937.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -564,10 +564,10 @@ 


	clock_gcc_mdss: qcom,gcc-mdss@1800000 {

		compatible = "qcom,gcc-mdss-8937";

		clocks = <&mdss_dsi0_pll clk_pixel_clk_src>,

			 <&mdss_dsi0_pll clk_byte_clk_src>,

			 <&mdss_dsi0_pll clk_pixel_clk_src>,

			 <&mdss_dsi0_pll clk_byte_clk_src>;

		clocks = <&mdss_dsi0_pll clk_dsi_pll0_pixel_clk_src>,

			 <&mdss_dsi0_pll clk_dsi_pll0_byte_clk_src>,

			 <&mdss_dsi1_pll clk_dsi_pll1_pixel_clk_src>,

			 <&mdss_dsi1_pll clk_dsi_pll1_byte_clk_src>;

		clock-names = "pixel_src", "byte_src", "pclk1_src",

				"byte1_src";

		#clock-cells = <1>;