Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ce46a9c4 authored by Ben Dooks's avatar Ben Dooks
Browse files

[ARM] S3C24XX: Split map.h into plat-s3c24xx and mach-s3c2410 



Split the map.h definitions into common S3C24XX code by
adding arch/arm/plat-s3c24xx/include/plat/map.h and
altering the machine specific header for the S3C24A0.

As we add a new <plat/map.h> we move the original one
in arch/arm/plat-s3c include directory to be called
map-base.h to distinguish the two files.

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
parent 1d4bab08

arch/arm/mach-s3c2410/include/mach/map.h

+3 −77
Original line number Diff line number Diff line
@@ -13,34 +13,20 @@ 
#ifndef __ASM_ARCH_MAP_H

#define __ASM_ARCH_MAP_H



#include <plat/map-base.h>

#include <plat/map.h>



#define S3C2410_ADDR(x)		S3C_ADDR(x)



/* interrupt controller is the first thing we put in, to make

 * the assembly code for the irq detection easier

 */

#define S3C24XX_VA_IRQ	   S3C_VA_IRQ

#define S3C2410_PA_IRQ	   (0x4A000000)

#define S3C24XX_SZ_IRQ	   SZ_1M



/* memory controller registers */

#define S3C24XX_VA_MEMCTRL S3C_VA_MEM

#define S3C2410_PA_MEMCTRL (0x48000000)

#define S3C24XX_SZ_MEMCTRL SZ_1M



/* USB host controller */

#define S3C2410_PA_USBHOST (0x49000000)

#define S3C24XX_SZ_USBHOST SZ_1M



/* DMA controller */

#define S3C2410_PA_DMA	   (0x4B000000)

#define S3C24XX_SZ_DMA	   SZ_1M



/* Clock and Power management */

#define S3C24XX_VA_CLKPWR  S3C_VA_SYS

#define S3C2410_PA_CLKPWR  (0x4C000000)

#define S3C24XX_SZ_CLKPWR  SZ_1M



/* LCD controller */

#define S3C2410_PA_LCD	   (0x4D000000)
@@ -48,48 +34,12 @@ 


/* NAND flash controller */

#define S3C2410_PA_NAND	   (0x4E000000)

#define S3C24XX_SZ_NAND	   SZ_1M



/* UARTs */

#define S3C24XX_VA_UART	   S3C_VA_UART

#define S3C2410_PA_UART	   (0x50000000)

#define S3C24XX_SZ_UART	   SZ_1M



/* Timers */

#define S3C24XX_VA_TIMER   S3C_VA_TIMER

#define S3C2410_PA_TIMER   (0x51000000)

#define S3C24XX_SZ_TIMER   SZ_1M



/* USB Device port */

#define S3C2410_PA_USBDEV  (0x52000000)

#define S3C24XX_SZ_USBDEV  SZ_1M



/* Watchdog */

#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG

#define S3C2410_PA_WATCHDOG (0x53000000)

#define S3C24XX_SZ_WATCHDOG SZ_1M



/* IIC hardware controller */

#define S3C2410_PA_IIC	   (0x54000000)

#define S3C24XX_SZ_IIC	   SZ_1M



/* IIS controller */

#define S3C2410_PA_IIS	   (0x55000000)

#define S3C24XX_SZ_IIS	   SZ_1M



/* GPIO ports */



/* the calculation for the VA of this must ensure that

 * it is the same distance apart from the UART in the

 * phsyical address space, as the initial mapping for the IO

 * is done as a 1:1 maping. This puts it (currently) at

 * 0xFA800000, which is not in the way of any current mapping

 * by the base system.

*/



#define S3C2410_PA_GPIO	   (0x56000000)

#define S3C24XX_VA_GPIO	   ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)

#define S3C24XX_SZ_GPIO	   SZ_1M



/* RTC */

#define S3C2410_PA_RTC	   (0x57000000)
@@ -97,15 +47,12 @@ 


/* ADC */

#define S3C2410_PA_ADC	   (0x58000000)

#define S3C24XX_SZ_ADC	   SZ_1M



/* SPI */

#define S3C2410_PA_SPI	   (0x59000000)

#define S3C24XX_SZ_SPI	   SZ_1M



/* SDI */

#define S3C2410_PA_SDI	   (0x5A000000)

#define S3C24XX_SZ_SDI	   SZ_1M



/* CAMIF */

#define S3C2440_PA_CAMIF   (0x4F000000)
@@ -120,13 +67,6 @@ 
#define S3C2443_PA_HSMMC   (0x4A800000)

#define S3C2443_SZ_HSMMC   (256)



/* ISA style IO, for each machine to sort out mappings for, if it

 * implements it. We reserve two 16M regions for ISA.

 */



#define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)

#define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)



/* physical addresses of all the chip-select areas */



#define S3C2410_CS0 (0x00000000)
@@ -158,21 +98,7 @@ 
#define S3C24XX_PA_RTC      S3C2410_PA_RTC

#define S3C24XX_PA_ADC      S3C2410_PA_ADC

#define S3C24XX_PA_SPI      S3C2410_PA_SPI



/* deal with the registers that move under the 2412/2413 */



#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)

#ifndef __ASSEMBLY__

extern void __iomem *s3c24xx_va_gpio2;

#endif

#ifdef CONFIG_CPU_S3C2412_ONLY

#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)

#else

#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2

#endif

#else

#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO

#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO

#endif

#define S3C24XX_PA_SDI      S3C2410_PA_SDI

#define S3C24XX_PA_NAND	    S3C2410_PA_NAND



#endif /* __ASM_ARCH_MAP_H */

arch/arm/mach-s3c24a0/include/mach/map.h

+5 −0
Original line number Diff line number Diff line
@@ -14,6 +14,9 @@ 
#ifndef __ASM_ARCH_24A0_MAP_H

#define __ASM_ARCH_24A0_MAP_H __FILE__



#include <plat/map-base.h>

#include <plat/map.h>



#define S3C24A0_PA_IO_BASE	(0x40000000)

#define S3C24A0_PA_CLKPWR	(0x40000000)

#define S3C24A0_PA_IRQ		(0x40200000)
@@ -74,5 +77,7 @@ 
#define S3C24XX_PA_RTC		S3C24A0_PA_RTC

#define S3C24XX_PA_ADC		S3C24A0_PA_ADC

#define S3C24XX_PA_SPI		S3C24A0_PA_SPI

#define S3C24XX_PA_SDI		S3C24A0_PA_SDI

#define S3C24XX_PA_NAND		S3C24A0_PA_NAND



#endif /* __ASM_ARCH_24A0_MAP_H */

arch/arm/plat-s3c24xx/devs.c

+4 −4
Original line number Diff line number Diff line
@@ -192,8 +192,8 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) 


static struct resource s3c_nand_resource[] = {

	[0] = {

		.start = S3C2410_PA_NAND,

		.end   = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1,

		.start = S3C24XX_PA_NAND,

		.end   = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1,

		.flags = IORESOURCE_MEM,

	}

};
@@ -382,8 +382,8 @@ struct platform_device s3c_device_adc = { 


static struct resource s3c_sdi_resource[] = {

	[0] = {

		.start = S3C2410_PA_SDI,

		.end   = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,

		.start = S3C24XX_PA_SDI,

		.end   = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1,

		.flags = IORESOURCE_MEM,

	},

	[1] = {

arch/arm/plat-s3c24xx/include/plat/map.h

0 → 100644
+99 −0
Original line number Diff line number Diff line 
/* linux/include/asm-arm/plat-s3c24xx/map.h

 *

 * Copyright (c) 2008 Simtec Electronics

 *	Ben Dooks <ben@simtec.co.uk>

 *

 * S3C24XX - Memory map definitions

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

*/



#ifndef __ASM_PLAT_S3C24XX_MAP_H

#define __ASM_PLAT_S3C24XX_MAP_H



/* interrupt controller is the first thing we put in, to make

 * the assembly code for the irq detection easier

 */

#define S3C24XX_VA_IRQ	   S3C_VA_IRQ

#define S3C2410_PA_IRQ	   (0x4A000000)

#define S3C24XX_SZ_IRQ	   SZ_1M



/* memory controller registers */

#define S3C24XX_VA_MEMCTRL S3C_VA_MEM

#define S3C2410_PA_MEMCTRL (0x48000000)

#define S3C24XX_SZ_MEMCTRL SZ_1M



/* UARTs */

#define S3C24XX_VA_UART	   S3C_VA_UART

#define S3C2410_PA_UART	   (0x50000000)

#define S3C24XX_SZ_UART	   SZ_1M



/* Timers */

#define S3C24XX_VA_TIMER   S3C_VA_TIMER

#define S3C2410_PA_TIMER   (0x51000000)

#define S3C24XX_SZ_TIMER   SZ_1M



/* Clock and Power management */

#define S3C24XX_VA_CLKPWR  S3C_VA_SYS

#define S3C24XX_SZ_CLKPWR  SZ_1M



/* USB Device port */

#define S3C2410_PA_USBDEV  (0x52000000)

#define S3C24XX_SZ_USBDEV  SZ_1M



/* Watchdog */

#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG

#define S3C2410_PA_WATCHDOG (0x53000000)

#define S3C24XX_SZ_WATCHDOG SZ_1M



/* Standard size definitions for peripheral blocks. */



#define S3C24XX_SZ_IIC		SZ_1M

#define S3C24XX_SZ_IIS		SZ_1M

#define S3C24XX_SZ_ADC		SZ_1M

#define S3C24XX_SZ_SPI		SZ_1M

#define S3C24XX_SZ_SDI		SZ_1M

#define S3C24XX_SZ_NAND		SZ_1M

#define S3C24XX_SZ_USBHOST	SZ_1M



/* GPIO ports */



/* the calculation for the VA of this must ensure that

 * it is the same distance apart from the UART in the

 * phsyical address space, as the initial mapping for the IO

 * is done as a 1:1 maping. This puts it (currently) at

 * 0xFA800000, which is not in the way of any current mapping

 * by the base system.

*/



#define S3C2410_PA_GPIO	   (0x56000000)

#define S3C24XX_VA_GPIO	   ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)

#define S3C24XX_SZ_GPIO	   SZ_1M





/* ISA style IO, for each machine to sort out mappings for, if it

 * implements it. We reserve two 16M regions for ISA.

 */



#define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)

#define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)



/* deal with the registers that move under the 2412/2413 */



#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)

#ifndef __ASSEMBLY__

extern void __iomem *s3c24xx_va_gpio2;

#endif

#ifdef CONFIG_CPU_S3C2412_ONLY

#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)

#else

#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2

#endif

#else

#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO

#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO

#endif



#endif /* __ASM_PLAT_S3C24XX_MAP_H */