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Commit cd9b3d04 authored by Wayne Boyer's avatar Wayne Boyer Committed by James Bottomley
Browse files

[SCSI] ipr: update PCI ID definitions for new adapters 



This patch updates some PCI ID definitions for new adapters based on the next
generation 64 bit IOA PCI interface chip.

Signed-off-by: default avatarWayne Boyer <wayneb@linux.vnet.ibm.com>
Acked-by: default avatarBrian King <brking@linux.vnet.ibm.com>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent 8a655229

drivers/scsi/ipr.c

+7 −7
Original line number Original line Diff line number Diff line
@@ -183,7 +183,7 @@ static const struct ipr_chip_t ipr_chip[] = { 
	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },

	{ PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },

	{ PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] }

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] }

};

};





static int ipr_max_bus_speeds [] = {

static int ipr_max_bus_speeds [] = {
@@ -9191,15 +9191,15 @@ static struct pci_device_id ipr_pci_table[] __devinitdata = { 
		PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C3, 0, 0, 0 },

		PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C3, 0, 0, 0 },

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,

		PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C4, 0, 0, 0 },

		PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C4, 0, 0, 0 },

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2,

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,

		PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B4, 0, 0, 0 },

		PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B4, 0, 0, 0 },

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2,

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,

		PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B1, 0, 0, 0 },

		PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B1, 0, 0, 0 },

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2,

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,

		PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C6, 0, 0, 0 },

		PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C6, 0, 0, 0 },

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2,

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,

		PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575D, 0, 0, 0 },

		PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C8, 0, 0, 0 },

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2,

	{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,

		PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CE, 0, 0, 0 },

		PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CE, 0, 0, 0 },

	{ }

	{ }

};

};

drivers/scsi/ipr.h

+2 −2
Original line number Original line Diff line number Diff line
@@ -58,7 +58,7 @@ 
#define PCI_DEVICE_ID_IBM_OBSIDIAN_E	0x0339

#define PCI_DEVICE_ID_IBM_OBSIDIAN_E	0x0339





#define PCI_DEVICE_ID_IBM_CROC_FPGA_E2          0x033D

#define PCI_DEVICE_ID_IBM_CROC_FPGA_E2          0x033D

#define PCI_DEVICE_ID_IBM_CROC_ASIC_E2          0x034A

#define PCI_DEVICE_ID_IBM_CROCODILE             0x034A





#define IPR_SUBS_DEV_ID_2780	0x0264

#define IPR_SUBS_DEV_ID_2780	0x0264

#define IPR_SUBS_DEV_ID_5702	0x0266

#define IPR_SUBS_DEV_ID_5702	0x0266
@@ -92,7 +92,7 @@ 
#define IPR_SUBS_DEV_ID_57B1    0x0355

#define IPR_SUBS_DEV_ID_57B1    0x0355





#define IPR_SUBS_DEV_ID_574D    0x0356

#define IPR_SUBS_DEV_ID_574D    0x0356

#define IPR_SUBS_DEV_ID_575D    0x035D

#define IPR_SUBS_DEV_ID_57C8    0x035D





#define IPR_NAME				"ipr"

#define IPR_NAME				"ipr"