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Commit cd8d70a1 authored by Patrick Daly's avatar Patrick Daly
Browse files

ARM: dts: msm: Add misc coresight components for mdmcalifornium 



Add STM, DEBUGUI, CTI, TPDM, and TPDA devices.

Change-Id: I8fec390efb8df0a483da4f94138bbef887d36481
Signed-off-by: default avatarPatrick Daly <pdaly@codeaurora.org>
parent 3dc73b07

arch/arm/boot/dts/qcom/mdmcalifornium-coresight.dtsi

+282 −0
Original line number Diff line number Diff line
@@ -187,4 +187,286 @@ 
			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	stm: stm@802000 {

		compatible = "arm,coresight-stm";

		reg = <0x802000 0x1000>,

		      <0x9280000 0x180000>;

		reg-names = "stm-base", "stm-data-base";



		coresight-id = <12>;

		coresight-name = "coresight-stm";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <7>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	dbgui: dbgui@86d000 {

		compatible = "qcom,coresight-dbgui";

		reg = <0x86d000 0x1000>;

		reg-names = "dbgui-base";



		coresight-id = <13>;

		coresight-name = "coresight-dbgui";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in1>;

		coresight-child-ports = <4>;



		qcom,dbgui-addr-offset = <0x30>;

		qcom,dbgui-data-offset = <0xb0>;

		qcom,dbgui-size = <0x20>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	tpda: tpda@803000 {

		compatible = "qcom,coresight-tpda";

		reg = <0x803000 0x1000>;

		reg-names = "tpda-base";



		coresight-id = <14>;

		coresight-name = "coresight-tpda";

		coresight-nr-inports = <32>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <6>;



		qcom,tpda-atid = <65>;

		qcom,cmb-elem-size = <0 8>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	tpda_modem: tpda@3003000 {

		compatible = "qcom,coresight-tpda";

		reg = <0x83b000 0x1000>;

		reg-names = "tpda-base";



		coresight-id = <15>;

		coresight-name = "coresight-tpda-modem";

		coresight-nr-inports = <32>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in1>;

		coresight-child-ports = <5>;



		qcom,tpda-atid = <66>;

		qcom,dsb-elem-size = <0 32>;

		qcom,cmb-elem-size = <0 8>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	tpdm_dcc: tpdm@864000 {

		compatible = "qcom,coresight-tpdm";

		reg = <0x864000 0x1000>;

		reg-names = "tpdm-base";



		coresight-id = <16>;

		coresight-name = "coresight-tpdm-dcc";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&tpda>;

		coresight-child-ports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	tpdm_modem: tpdm@83a000 {

		compatible = "qcom,coresight-tpdm";

		reg = <0x83a000 0x1000>;

		reg-names = "tpdm-base";



		coresight-id = <17>;

		coresight-name = "coresight-tpdm-modem";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&tpda_modem>;

		coresight-child-ports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti0: cti@810000 {

		compatible = "arm,coresight-cti";

		reg = <0x810000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <18>;

		coresight-name = "coresight-cti0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti1: cti@811000 {

		compatible = "arm,coresight-cti";

		reg = <0x811000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <19>;

		coresight-name = "coresight-cti1";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti2: cti@812000 {

		compatible = "arm,coresight-cti";

		reg = <0x812000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <20>;

		coresight-name = "coresight-cti2";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti3: cti@813000 {

		compatible = "arm,coresight-cti";

		reg = <0x813000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <21>;

		coresight-name = "coresight-cti3";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti4: cti@814000 {

		compatible = "arm,coresight-cti";

		reg = <0x814000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <22>;

		coresight-name = "coresight-cti4";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti5: cti@815000 {

		compatible = "arm,coresight-cti";

		reg = <0x815000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <23>;

		coresight-name = "coresight-cti5";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti6: cti@816000 {

		compatible = "arm,coresight-cti";

		reg = <0x816000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <24>;

		coresight-name = "coresight-cti6";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_modem_cpu0: cti@8390000 {

		compatible = "arm,coresight-cti";

		reg = <0x8390000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <25>;

		coresight-name = "coresight-cti-modem-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_pmu_cpu0: cti@841000 {

		compatible = "arm,coresight-cti";

		reg = <0x841000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <26>;

		coresight-name = "coresight-cti-pmu-cpu0";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu0: cti@843000 {

		compatible = "arm,coresight-cti";

		reg = <0x843000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <27>;

		coresight-name = "coresight-cti-cpu0";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	hwevent: hwevent@86c000 {

		compatible = "qcom,coresight-hwevent";

		reg =   <0x0086c000 0x148>,

			<0x00801020 0x10>,

			<0x08af8860 0x4>,

			<0x0200c000 0x4>,

			<0x0200c008 0x20>,

			<0x08b05014 0x4>,

			<0x0408200c 0x4>;

		reg-names = "qdss-wrapper",

			    "stm",

			    "usb30",

			    "spmi-test",

			    "spmi-events",

			    "usb30-bam",

			    "mss";



		coresight-id = <28>;

		coresight-name = "coresight-hwevent";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};

};