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Commit ccd6a131 authored by Gregory CLEMENT's avatar Gregory CLEMENT Committed by Jason Cooper
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ARM: mvebu: remove the address parameter for ll_set_cpu_coherent 



In order to be able to deal with the MMU enabled and the MMU disabled
cases, the base address of the coherency registers was passed to the
function. The address by itself was not interesting as it can't change
for a given SoC, the only thing we need is to have a distinction
between the physical or the virtual address.

This patch add a check of the MMU bit to choose the accurate address,
then the calling function doesn't have to pass this information.

Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-3-git-send-email-gregory.clement@free-electrons.com


Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent b4bca249

arch/arm/mach-mvebu/coherency.c

+3 −3
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ 
#include "coherency.h"



unsigned long coherency_phys_base;

static void __iomem *coherency_base;

void __iomem *coherency_base;

static void __iomem *coherency_cpu_base;



/* Coherency fabric registers */
@@ -61,7 +61,7 @@ static struct of_device_id of_coherency_table[] = { 
};



/* Function defined in coherency_ll.S */

int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);

int ll_set_cpu_coherent(unsigned int hw_cpu_id);



int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id)

{
@@ -71,7 +71,7 @@ int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id) 
		return 1;

	}



	return ll_set_cpu_coherent(coherency_base, hw_cpu_id);

	return ll_set_cpu_coherent(hw_cpu_id);

}



/*

arch/arm/mach-mvebu/coherency_ll.S

+20 −2
Original line number Diff line number Diff line
@@ -21,13 +21,27 @@ 
#define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4



#include <asm/assembler.h>

#include <asm/cp15.h>



	.text

/*

 * r0: Coherency fabric base register address

 * r1: HW CPU id

 * r0: HW CPU id

 */

ENTRY(ll_set_cpu_coherent)

	mrc	p15, 0, r1, c1, c0, 0

	tst	r1, #CR_M @ Check MMU bit enabled

	bne	1f



	/* use physical address of the coherency register*/

	adr	r0, 3f

	ldr	r3, [r0]

	ldr	r0, [r0, r3]

	b	2f

1:

	/* use virtual address of the coherency register*/

	ldr	r0, =coherency_base

	ldr	r0, [r0]

2:

	/* Create bit by cpu index */

	mov	r3, #(1 << 24)

	lsl	r1, r3, r1
@@ -56,3 +70,7 @@ ARM_BE8(rev r1, r1) 
	mov	r0, #0

	mov	pc, lr

ENDPROC(ll_set_cpu_coherent)



	.align 2

3:

	.long	coherency_phys_base - .

arch/arm/mach-mvebu/headsmp.S

+0 −9
Original line number Diff line number Diff line
@@ -31,11 +31,6 @@ 
ENTRY(armada_xp_secondary_startup)

 ARM_BE8(setend	be )			@ go BE8 if entered LE



	/* Get coherency fabric base physical address */

	adr	r0, 1f

	ldr	r1, [r0]

	ldr	r0, [r0, r1]



	/* Read CPU id */

	mrc     p15, 0, r1, c0, c0, 5

	and     r1, r1, #0xF
@@ -45,7 +40,3 @@ ENTRY(armada_xp_secondary_startup) 
	b	secondary_startup



ENDPROC(armada_xp_secondary_startup)
 


	.align 2

1:

	.long	coherency_phys_base - .